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https://github.com/ARM-software/arm-trusted-firmware.git
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c64873ab94
BL2_BASE, BL31_BASE, and BL32_BASE are defined in platform_def.h, that is, determined at link-time. On the other hand, BL2_END, BL31_END, and BL32_END are derived from the symbols produced by the linker scripts. So, they are fixed-up at run-time if ENABLE_PIE is enabled. To make it work in a position-indepenent manner, use BL_CODE_BASE and BL_END, both of which are relocatable. Change-Id: Ic179a7c60eb64c5f3024b178690b3ac7cbd7521b Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
84 lines
1.8 KiB
C
84 lines
1.8 KiB
C
/*
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <platform_def.h>
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#include <arch.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/console.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_mmu_helpers.h>
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#include <plat/common/platform.h>
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#include "uniphier.h"
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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assert(sec_state_is_valid(type));
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return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info;
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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void *from_bl2;
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from_bl2 = (void *)arg0;
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bl_params_node_t *bl_params = ((bl_params_t *)from_bl2)->head;
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uniphier_console_setup();
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while (bl_params) {
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if (bl_params->image_id == BL32_IMAGE_ID)
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bl32_image_ep_info = *bl_params->ep_info;
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if (bl_params->image_id == BL33_IMAGE_ID)
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bl33_image_ep_info = *bl_params->ep_info;
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bl_params = bl_params->next_params_info;
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}
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if (bl33_image_ep_info.pc == 0)
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panic();
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}
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#define UNIPHIER_SYS_CNTCTL_BASE 0x60E00000
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void bl31_platform_setup(void)
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{
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unsigned int soc;
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soc = uniphier_get_soc_id();
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if (soc == UNIPHIER_SOC_UNKNOWN) {
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ERROR("unsupported SoC\n");
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plat_error_handler(-ENOTSUP);
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}
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uniphier_cci_init(soc);
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uniphier_cci_enable();
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/* Initialize the GIC driver, cpu and distributor interfaces */
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uniphier_gic_driver_init(soc);
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uniphier_gic_init();
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/* Enable and initialize the System level generic timer */
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mmio_write_32(UNIPHIER_SYS_CNTCTL_BASE + CNTCR_OFF,
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CNTCR_FCREQ(0U) | CNTCR_EN);
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}
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void bl31_plat_arch_setup(void)
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{
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uniphier_mmap_setup();
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enable_mmu_el3(0);
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}
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