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bd063a73a8
Neoverse Demeter CPU has been renamed to Neoverse V2 CPU. Correspondingly, update the CPU library, file names and other references to use the updated IP name. Signed-off-by: Joel Goddard <joel.goddard@arm.com> Change-Id: Ia4bf45bf47807c06f4c966861230faea420d088f
112 lines
2.9 KiB
ArmAsm
112 lines
2.9 KiB
ArmAsm
/*
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <neoverse_v2.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2
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#endif /* WORKAROUND_CVE_2022_23960 */
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func neoverse_v2_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1
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orr x0, x0, #NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc neoverse_v2_core_pwr_dwn
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2022_23960
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func neoverse_v2_reset_func
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/* Disable speculative loads */
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msr SSBS, xzr
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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/*
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* The Neoverse V2 vectors are overridden to apply
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* errata mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_neoverse_v2
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
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isb
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ret
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endfunc neoverse_v2_reset_func
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#if REPORT_ERRATA
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/*
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* Errata printing function for Neoverse V2. Must follow AAPCS.
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*/
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func neoverse_v2_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata WORKAROUND_CVE_2022_23960, neoverse_v2, cve_2022_23960
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ldp x8, x30, [sp], #16
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ret
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endfunc neoverse_v2_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides Neoverse V2-
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* specific register information for crash
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* reporting. It needs to return with x6
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* pointing to a list of register names in ascii
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* and x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.neoverse_v2_regs, "aS"
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neoverse_v2_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func neoverse_v2_cpu_reg_dump
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adr x6, neoverse_v2_regs
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mrs x8, NEOVERSE_V2_CPUECTLR_EL1
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ret
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endfunc neoverse_v2_cpu_reg_dump
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declare_cpu_ops neoverse_v2, NEOVERSE_V2_MIDR, \
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neoverse_v2_reset_func, \
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neoverse_v2_core_pwr_dwn
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