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https://github.com/ARM-software/arm-trusted-firmware.git
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bbf8f6f95b
The upcoming Firmware Update feature needs transitioning across Secure/Normal worlds to complete the FWU process and hence requires context management code to perform this task. Currently context management code is part of BL31 stage only. This patch moves the code from (include)/bl31 to (include)/common. Some function declarations/definitions and macros have also moved to different files to help code sharing. Change-Id: I3858b08aecdb76d390765ab2b099f457873f7b0c
229 lines
5.8 KiB
ArmAsm
229 lines
5.8 KiB
ArmAsm
/*
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* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <bl_common.h>
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.globl bl1_exceptions
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.section .vectors, "ax"; .align 11
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/* -----------------------------------------------------
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* Very simple stackless exception handlers used by BL1.
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* -----------------------------------------------------
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*/
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.align 7
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bl1_exceptions:
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/* -----------------------------------------------------
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* Current EL with SP0 : 0x0 - 0x200
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* -----------------------------------------------------
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*/
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SynchronousExceptionSP0:
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mov x0, #SYNC_EXCEPTION_SP_EL0
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bl plat_report_exception
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b SynchronousExceptionSP0
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check_vector_size SynchronousExceptionSP0
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.align 7
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IrqSP0:
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mov x0, #IRQ_SP_EL0
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bl plat_report_exception
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b IrqSP0
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check_vector_size IrqSP0
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.align 7
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FiqSP0:
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mov x0, #FIQ_SP_EL0
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bl plat_report_exception
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b FiqSP0
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check_vector_size FiqSP0
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.align 7
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SErrorSP0:
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mov x0, #SERROR_SP_EL0
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bl plat_report_exception
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b SErrorSP0
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check_vector_size SErrorSP0
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/* -----------------------------------------------------
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* Current EL with SPx: 0x200 - 0x400
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* -----------------------------------------------------
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*/
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.align 7
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SynchronousExceptionSPx:
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mov x0, #SYNC_EXCEPTION_SP_ELX
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bl plat_report_exception
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b SynchronousExceptionSPx
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check_vector_size SynchronousExceptionSPx
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.align 7
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IrqSPx:
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mov x0, #IRQ_SP_ELX
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bl plat_report_exception
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b IrqSPx
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check_vector_size IrqSPx
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.align 7
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FiqSPx:
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mov x0, #FIQ_SP_ELX
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bl plat_report_exception
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b FiqSPx
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check_vector_size FiqSPx
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.align 7
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SErrorSPx:
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mov x0, #SERROR_SP_ELX
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bl plat_report_exception
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b SErrorSPx
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check_vector_size SErrorSPx
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/* -----------------------------------------------------
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* Lower EL using AArch64 : 0x400 - 0x600
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* -----------------------------------------------------
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*/
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.align 7
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SynchronousExceptionA64:
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/* Enable the SError interrupt */
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msr daifclr, #DAIF_ABT_BIT
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/* Expect only SMC exceptions */
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mrs x19, esr_el3
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ubfx x20, x19, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x20, #EC_AARCH64_SMC
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b.ne unexpected_sync_exception
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b smc_handler64
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check_vector_size SynchronousExceptionA64
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.align 7
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IrqA64:
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mov x0, #IRQ_AARCH64
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bl plat_report_exception
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b IrqA64
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check_vector_size IrqA64
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.align 7
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FiqA64:
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mov x0, #FIQ_AARCH64
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bl plat_report_exception
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b FiqA64
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check_vector_size FiqA64
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.align 7
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SErrorA64:
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mov x0, #SERROR_AARCH64
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bl plat_report_exception
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b SErrorA64
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check_vector_size SErrorA64
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/* -----------------------------------------------------
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* Lower EL using AArch32 : 0x600 - 0x800
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* -----------------------------------------------------
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*/
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.align 7
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SynchronousExceptionA32:
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mov x0, #SYNC_EXCEPTION_AARCH32
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bl plat_report_exception
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b SynchronousExceptionA32
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check_vector_size SynchronousExceptionA32
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.align 7
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IrqA32:
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mov x0, #IRQ_AARCH32
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bl plat_report_exception
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b IrqA32
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check_vector_size IrqA32
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.align 7
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FiqA32:
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mov x0, #FIQ_AARCH32
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bl plat_report_exception
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b FiqA32
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check_vector_size FiqA32
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.align 7
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SErrorA32:
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mov x0, #SERROR_AARCH32
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bl plat_report_exception
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b SErrorA32
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check_vector_size SErrorA32
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func smc_handler64
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/* ---------------------------------------------------------------------
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* Only a single SMC exception from BL2 to ask BL1 to pass EL3 control
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* to BL31 is expected here. It expects:
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* - X0 with RUN_IMAGE SMC function ID;
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* - X1 with the address of a entry_point_info_t structure describing
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* the BL31 entrypoint.
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* ---------------------------------------------------------------------
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*/
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mov x19, x0
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mov x20, x1
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mov x0, #RUN_IMAGE
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cmp x19, x0
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b.ne unexpected_sync_exception
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mov x0, x20
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bl bl1_print_bl31_ep_info
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ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
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msr elr_el3, x0
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msr spsr_el3, x1
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ubfx x0, x1, #MODE_EL_SHIFT, #2
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cmp x0, #MODE_EL3
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b.ne unexpected_sync_exception
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bl disable_mmu_icache_el3
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tlbi alle3
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#if SPIN_ON_BL1_EXIT
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bl print_debug_loop_message
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debug_loop:
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b debug_loop
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#endif
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mov x0, x20
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bl bl1_plat_prepare_exit
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ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
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ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
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ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
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ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
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eret
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endfunc smc_handler64
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unexpected_sync_exception:
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mov x0, #SYNC_EXCEPTION_AARCH64
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bl plat_report_exception
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wfi
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b unexpected_sync_exception
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