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https://github.com/ARM-software/arm-trusted-firmware.git
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Migrate Marvell platforms from legacy console API to multi-console API. Change-Id: I647f5f49148b463a257a747af05b5f0c967f267c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
132 lines
3.6 KiB
C
132 lines
3.6 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <console.h>
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#include <debug.h>
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#include <desc_image_load.h>
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#include <marvell_def.h>
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#include <platform_def.h>
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#include <plat_marvell.h>
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#include <string.h>
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#include <utils.h>
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/* Data structure which holds the extents of the trusted SRAM for BL2 */
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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/* Weak definitions may be overridden in specific MARVELL standard platform */
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#pragma weak bl2_early_platform_setup2
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#pragma weak bl2_platform_setup
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#pragma weak bl2_plat_arch_setup
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#pragma weak bl2_plat_sec_mem_layout
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meminfo_t *bl2_plat_sec_mem_layout(void)
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{
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return &bl2_tzram_layout;
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}
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/*****************************************************************************
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* BL1 has passed the extents of the trusted SRAM that should be visible to BL2
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* in x0. This memory layout is sitting at the base of the free trusted SRAM.
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* Copy it to a safe location before its reclaimed by later BL2 functionality.
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*****************************************************************************
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*/
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void marvell_bl2_early_platform_setup(meminfo_t *mem_layout)
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{
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/* Initialize the console to provide early debug support */
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marvell_console_boot_init();
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/* Setup the BL2 memory layout */
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bl2_tzram_layout = *mem_layout;
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/* Initialise the IO layer and register platform IO devices */
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plat_marvell_io_setup();
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}
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void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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struct meminfo *mem_layout = (struct meminfo *)arg1;
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marvell_bl2_early_platform_setup(mem_layout);
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}
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void bl2_platform_setup(void)
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{
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/* Nothing to do */
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}
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/*****************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this is only initializes the mmu in a quick and dirty way.
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*****************************************************************************
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*/
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void marvell_bl2_plat_arch_setup(void)
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{
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marvell_setup_page_tables(bl2_tzram_layout.total_base,
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bl2_tzram_layout.total_size,
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BL_CODE_BASE,
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BL_CODE_END,
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BL_RO_DATA_BASE,
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BL_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END
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#endif
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);
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enable_mmu_el1(0);
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}
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void bl2_plat_arch_setup(void)
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{
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marvell_bl2_plat_arch_setup();
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}
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int marvell_bl2_handle_post_image_load(unsigned int image_id)
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{
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int err = 0;
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bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
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assert(bl_mem_params);
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switch (image_id) {
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case BL33_IMAGE_ID:
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/* BL33 expects to receive the primary CPU MPID (through r0) */
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bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
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bl_mem_params->ep_info.spsr = marvell_get_spsr_for_bl33_entry();
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break;
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#ifdef SCP_BL2_BASE
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case SCP_BL2_IMAGE_ID:
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/* The subsequent handling of SCP_BL2 is platform specific */
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err = bl2_plat_handle_scp_bl2(&bl_mem_params->image_info);
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if (err) {
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WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
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}
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break;
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#endif
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default:
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/* Do nothing in default case */
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break;
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}
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return err;
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}
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/*******************************************************************************
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* This function can be used by the platforms to update/use image
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* information for given `image_id`.
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******************************************************************************/
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int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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return marvell_bl2_handle_post_image_load(image_id);
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}
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