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https://github.com/ARM-software/arm-trusted-firmware.git
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ba597da7fd
This patch introduces the shared Mbed TLS heap optimisation for Arm platforms. The objective is the Mbed TLS heap to be shared between BL1 and BL2 so as to not allocate the heap memory twice. To achieve that, the patch introduces all the necessary helpers for implementing this optimisation. It also applies it for FVP. Change-Id: I6d85eaa1361517b7490956b2ac50f5fa0d0bb008 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
410 lines
10 KiB
C
410 lines
10 KiB
C
/*
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* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arm_config.h>
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#include <arm_def.h>
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#include <arm_spm_def.h>
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#include <arm_xlat_tables.h>
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#include <assert.h>
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#include <cci.h>
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#include <ccn.h>
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#include <debug.h>
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#include <gicv2.h>
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#include <mmio.h>
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#include <plat_arm.h>
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#include <platform.h>
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#include <secure_partition.h>
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#include <v2m_def.h>
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#include "../fvp_def.h"
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#include "fvp_private.h"
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/* Defines for GIC Driver build time selection */
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#define FVP_GICV2 1
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#define FVP_GICV3 2
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#define FVP_GICV3_LEGACY 3
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/*******************************************************************************
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* arm_config holds the characteristics of the differences between the three FVP
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* platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
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* at each boot stage by the primary before enabling the MMU (to allow
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* interconnect configuration) & used thereafter. Each BL will have its own copy
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* to allow independent operation.
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******************************************************************************/
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arm_config_t arm_config;
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#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
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DEVICE0_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
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DEVICE1_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/*
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* Need to be mapped with write permissions in order to set a new non-volatile
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* counter value.
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*/
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#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
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DEVICE2_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/*
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* Table of memory regions for various BL stages to map using the MMU.
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* This doesn't include Trusted SRAM as arm_setup_page_tables() already
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* takes care of mapping it.
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*
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* The flash needs to be mapped as writable in order to erase the FIP's Table of
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* Contents in case of unrecoverable error (see plat_error_handler()).
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*/
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#ifdef IMAGE_BL1
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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V2M_MAP_FLASH0_RW,
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V2M_MAP_IOFPGA,
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MAP_DEVICE0,
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MAP_DEVICE1,
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#if TRUSTED_BOARD_BOOT
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/* To access the Root of Trust Public Key registers. */
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MAP_DEVICE2,
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/* Map DRAM to authenticate NS_BL2U image. */
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ARM_MAP_NS_DRAM1,
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#endif
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{0}
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};
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#endif
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#ifdef IMAGE_BL2
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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V2M_MAP_FLASH0_RW,
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V2M_MAP_IOFPGA,
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MAP_DEVICE0,
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MAP_DEVICE1,
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ARM_MAP_NS_DRAM1,
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#ifdef AARCH64
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ARM_MAP_DRAM2,
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#endif
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#ifdef SPD_tspd
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ARM_MAP_TSP_SEC_MEM,
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#endif
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#if TRUSTED_BOARD_BOOT
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/* To access the Root of Trust Public Key registers. */
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MAP_DEVICE2,
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#if LOAD_IMAGE_V2 && !BL2_AT_EL3
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ARM_MAP_BL1_RW,
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#endif /* LOAD_IMAGE_V2 && !BL2_AT_EL3 */
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#endif /* TRUSTED_BOARD_BOOT */
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#if ENABLE_SPM
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ARM_SP_IMAGE_MMAP,
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#endif
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#if ARM_BL31_IN_DRAM
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ARM_MAP_BL31_SEC_DRAM,
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#endif
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#ifdef SPD_opteed
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ARM_MAP_OPTEE_CORE_MEM,
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ARM_OPTEE_PAGEABLE_LOAD_MEM,
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#endif
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{0}
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};
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#endif
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#ifdef IMAGE_BL2U
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const mmap_region_t plat_arm_mmap[] = {
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MAP_DEVICE0,
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V2M_MAP_IOFPGA,
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{0}
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};
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#endif
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#ifdef IMAGE_BL31
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const mmap_region_t plat_arm_mmap[] = {
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ARM_MAP_SHARED_RAM,
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ARM_MAP_EL3_TZC_DRAM,
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V2M_MAP_IOFPGA,
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MAP_DEVICE0,
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MAP_DEVICE1,
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ARM_V2M_MAP_MEM_PROTECT,
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#if ENABLE_SPM
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ARM_SPM_BUF_EL3_MMAP,
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#endif
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{0}
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};
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#if ENABLE_SPM && defined(IMAGE_BL31)
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const mmap_region_t plat_arm_secure_partition_mmap[] = {
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V2M_MAP_IOFPGA_EL0, /* for the UART */
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MAP_REGION_FLAT(DEVICE0_BASE, \
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DEVICE0_SIZE, \
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MT_DEVICE | MT_RO | MT_SECURE | MT_USER),
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ARM_SP_IMAGE_MMAP,
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ARM_SP_IMAGE_NS_BUF_MMAP,
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ARM_SP_IMAGE_RW_MMAP,
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ARM_SPM_BUF_EL0_MMAP,
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{0}
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};
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#endif
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#endif
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#ifdef IMAGE_BL32
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const mmap_region_t plat_arm_mmap[] = {
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#ifdef AARCH32
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ARM_MAP_SHARED_RAM,
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ARM_V2M_MAP_MEM_PROTECT,
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#endif
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V2M_MAP_IOFPGA,
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MAP_DEVICE0,
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MAP_DEVICE1,
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{0}
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};
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#endif
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ARM_CASSERT_MMAP
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#if FVP_INTERCONNECT_DRIVER != FVP_CCN
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static const int fvp_cci400_map[] = {
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PLAT_FVP_CCI400_CLUS0_SL_PORT,
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PLAT_FVP_CCI400_CLUS1_SL_PORT,
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};
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static const int fvp_cci5xx_map[] = {
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PLAT_FVP_CCI5XX_CLUS0_SL_PORT,
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PLAT_FVP_CCI5XX_CLUS1_SL_PORT,
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};
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static unsigned int get_interconnect_master(void)
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{
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unsigned int master;
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u_register_t mpidr;
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mpidr = read_mpidr_el1();
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master = (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) ?
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MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr);
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assert(master < FVP_CLUSTER_COUNT);
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return master;
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}
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#endif
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#if ENABLE_SPM && defined(IMAGE_BL31)
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/*
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* Boot information passed to a secure partition during initialisation. Linear
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* indices in MP information will be filled at runtime.
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*/
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static secure_partition_mp_info_t sp_mp_info[] = {
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[0] = {0x80000000, 0},
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[1] = {0x80000001, 0},
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[2] = {0x80000002, 0},
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[3] = {0x80000003, 0},
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[4] = {0x80000100, 0},
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[5] = {0x80000101, 0},
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[6] = {0x80000102, 0},
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[7] = {0x80000103, 0},
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};
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const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
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.h.type = PARAM_SP_IMAGE_BOOT_INFO,
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.h.version = VERSION_1,
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.h.size = sizeof(secure_partition_boot_info_t),
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.h.attr = 0,
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.sp_mem_base = ARM_SP_IMAGE_BASE,
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.sp_mem_limit = ARM_SP_IMAGE_LIMIT,
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.sp_image_base = ARM_SP_IMAGE_BASE,
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.sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
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.sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
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.sp_ns_comm_buf_base = ARM_SP_IMAGE_NS_BUF_BASE,
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.sp_shared_buf_base = PLAT_SPM_BUF_BASE,
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.sp_image_size = ARM_SP_IMAGE_SIZE,
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.sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
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.sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
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.sp_ns_comm_buf_size = ARM_SP_IMAGE_NS_BUF_SIZE,
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.sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
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.num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
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.num_cpus = PLATFORM_CORE_COUNT,
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.mp_info = &sp_mp_info[0],
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};
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const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
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{
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return plat_arm_secure_partition_mmap;
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}
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const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
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void *cookie)
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{
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return &plat_arm_secure_partition_boot_info;
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}
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#endif
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/*******************************************************************************
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* A single boot loader stack is expected to work on both the Foundation FVP
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* models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
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* SYS_ID register provides a mechanism for detecting the differences between
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* these platforms. This information is stored in a per-BL array to allow the
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* code to take the correct path.Per BL platform configuration.
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******************************************************************************/
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void fvp_config_setup(void)
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{
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unsigned int rev, hbi, bld, arch, sys_id;
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sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
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rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
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hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
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bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
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arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
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if (arch != ARCH_MODEL) {
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ERROR("This firmware is for FVP models\n");
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panic();
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}
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/*
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* The build field in the SYS_ID tells which variant of the GIC
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* memory is implemented by the model.
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*/
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switch (bld) {
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case BLD_GIC_VE_MMAP:
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ERROR("Legacy Versatile Express memory map for GIC peripheral"
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" is not supported\n");
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panic();
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break;
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case BLD_GIC_A53A57_MMAP:
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break;
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default:
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ERROR("Unsupported board build %x\n", bld);
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panic();
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}
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/*
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* The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
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* for the Foundation FVP.
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*/
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switch (hbi) {
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case HBI_FOUNDATION_FVP:
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arm_config.flags = 0;
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/*
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* Check for supported revisions of Foundation FVP
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* Allow future revisions to run but emit warning diagnostic
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*/
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switch (rev) {
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case REV_FOUNDATION_FVP_V2_0:
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case REV_FOUNDATION_FVP_V2_1:
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case REV_FOUNDATION_FVP_v9_1:
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case REV_FOUNDATION_FVP_v9_6:
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break;
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default:
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WARN("Unrecognized Foundation FVP revision %x\n", rev);
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break;
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}
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break;
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case HBI_BASE_FVP:
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arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC);
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/*
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* Check for supported revisions
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* Allow future revisions to run but emit warning diagnostic
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*/
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switch (rev) {
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case REV_BASE_FVP_V0:
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arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400;
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break;
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case REV_BASE_FVP_REVC:
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arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 |
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ARM_CONFIG_FVP_HAS_CCI5XX);
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break;
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default:
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WARN("Unrecognized Base FVP revision %x\n", rev);
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break;
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}
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break;
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default:
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ERROR("Unsupported board HBI number 0x%x\n", hbi);
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panic();
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}
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/*
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* We assume that the presence of MT bit, and therefore shifted
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* affinities, is uniform across the platform: either all CPUs, or no
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* CPUs implement it.
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*/
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if (read_mpidr_el1() & MPIDR_MT_MASK)
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arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF;
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}
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void fvp_interconnect_init(void)
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{
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#if FVP_INTERCONNECT_DRIVER == FVP_CCN
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if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
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ERROR("Unrecognized CCN variant detected. Only CCN-502"
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" is supported");
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panic();
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}
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plat_arm_interconnect_init();
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#else
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uintptr_t cci_base = 0;
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const int *cci_map = 0;
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unsigned int map_size = 0;
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if (!(arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
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ARM_CONFIG_FVP_HAS_CCI5XX))) {
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return;
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}
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/* Initialize the right interconnect */
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if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) {
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cci_base = PLAT_FVP_CCI5XX_BASE;
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cci_map = fvp_cci5xx_map;
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map_size = ARRAY_SIZE(fvp_cci5xx_map);
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} else if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) {
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cci_base = PLAT_FVP_CCI400_BASE;
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cci_map = fvp_cci400_map;
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map_size = ARRAY_SIZE(fvp_cci400_map);
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}
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assert(cci_base);
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assert(cci_map);
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cci_init(cci_base, cci_map, map_size);
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#endif
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}
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void fvp_interconnect_enable(void)
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{
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#if FVP_INTERCONNECT_DRIVER == FVP_CCN
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plat_arm_interconnect_enter_coherency();
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#else
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unsigned int master;
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if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
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ARM_CONFIG_FVP_HAS_CCI5XX)) {
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master = get_interconnect_master();
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cci_enable_snoop_dvm_reqs(master);
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}
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#endif
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}
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void fvp_interconnect_disable(void)
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{
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#if FVP_INTERCONNECT_DRIVER == FVP_CCN
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plat_arm_interconnect_exit_coherency();
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#else
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unsigned int master;
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if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
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ARM_CONFIG_FVP_HAS_CCI5XX)) {
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master = get_interconnect_master();
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cci_disable_snoop_dvm_reqs(master);
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}
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#endif
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}
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#if TRUSTED_BOARD_BOOT && LOAD_IMAGE_V2
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int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
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{
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assert(heap_addr != NULL);
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assert(heap_size != NULL);
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return arm_get_mbedtls_heap(heap_addr, heap_size);
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}
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#endif
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