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https://github.com/ARM-software/arm-trusted-firmware.git
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b7c6529c41
This is used as a table index, and already compared with an unsigned int: block_dev_count. Signed-off-by: Yann Gautier <yann.gautier@st.com>
170 lines
5.3 KiB
C
170 lines
5.3 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <common_def.h>
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#include <gic_common.h>
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#include <interrupt_props.h>
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#include <tbbr/tbbr_img_def.h>
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#include <utils_def.h>
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#include "hi3798cv200.h"
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#include "poplar_layout.h" /* BL memory region sizes, etc */
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define POPLAR_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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#define POPLAR_CRASH_UART_BASE PL011_UART0_BASE
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#define POPLAR_CRASH_UART_CLK_IN_HZ PL011_UART0_CLK_IN_HZ
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#define POPLAR_CONSOLE_BAUDRATE PL011_BAUDRATE
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/* Generic platform constants */
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#define PLATFORM_STACK_SIZE (0x800)
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#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
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#define BOOT_EMMC_NAME "l-loader.bin"
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#define PLATFORM_CACHE_LINE_SIZE (64)
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#define PLATFORM_CLUSTER_COUNT (1)
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#define PLATFORM_CORE_COUNT (4)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER (4)
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/* IO framework user */
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#define MAX_IO_DEVICES (4)
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#define MAX_IO_HANDLES (4)
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#define MAX_IO_BLOCK_DEVICES U(2)
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/* Memory size options */
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#define POPLAR_DRAM_SIZE_1G 0
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#define POPLAR_DRAM_SIZE_2G 1
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/* Memory map related constants */
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#define DDR_BASE (0x00000000)
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#if (POPLAR_DRAM_SIZE_ID == POPLAR_DRAM_SIZE_2G)
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#define DDR_SIZE (0x80000000)
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#elif (POPLAR_DRAM_SIZE_ID == POPLAR_DRAM_SIZE_1G)
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#define DDR_SIZE (0x40000000)
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#else
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#error "Currently unsupported POPLAR_DRAM_SIZE_ID value"
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#endif
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#define DEVICE_BASE (0xF0000000)
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#define DEVICE_SIZE (0x0F000000)
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#define TEE_SEC_MEM_BASE (0x70000000)
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#define TEE_SEC_MEM_SIZE (0x10000000)
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/* Memory location options for TSP */
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#define POPLAR_SRAM_ID 0
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#define POPLAR_DRAM_ID 1
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/*
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* DDR for OP-TEE (26MB from 0x02400000 -0x04000000) is divided in several
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* regions:
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* - Secure DDR (default is the top 16MB) used by OP-TEE
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* - Non-secure DDR (4MB) reserved for OP-TEE's future use
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* - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
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* - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
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*/
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#define DDR_SEC_SIZE 0x01000000
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#define DDR_SEC_BASE 0x03000000
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/*
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* BL3-2 specific defines.
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*/
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/*
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* The TSP currently executes from TZC secured area of DRAM.
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*/
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#define BL32_DRAM_BASE 0x03000000
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#define BL32_DRAM_LIMIT 0x04000000
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#ifdef SPD_opteed
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/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
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#define POPLAR_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
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#define POPLAR_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - POPLAR_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x03C0_0000 */
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#endif
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#if (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_DRAM_ID)
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#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
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#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
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#define BL32_BASE BL32_DRAM_BASE
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#define BL32_LIMIT BL32_DRAM_LIMIT
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#elif (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_SRAM_ID)
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#error "SRAM storage of TSP payload is currently unsupported"
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#else
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#error "Currently unsupported POPLAR_TSP_LOCATION_ID value"
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#endif
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/* BL32 is mandatory in AArch32 */
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#ifndef AARCH32
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#ifdef SPD_none
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#undef BL32_BASE
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#endif /* SPD_none */
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#endif
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#define POPLAR_EMMC_DATA_BASE U(0x02200000)
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#define POPLAR_EMMC_DATA_SIZE EMMC_DESC_SIZE
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#define POPLAR_EMMC_DESC_BASE (POPLAR_EMMC_DATA_BASE + POPLAR_EMMC_DATA_SIZE)
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#define POPLAR_EMMC_DESC_SIZE EMMC_DESC_SIZE
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#define PLAT_POPLAR_NS_IMAGE_OFFSET 0x37000000
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/* Page table and MMU setup constants */
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define MAX_XLAT_TABLES (4)
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#define MAX_MMAP_REGIONS (16)
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#define CACHE_WRITEBACK_SHIFT (6)
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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/* Power states */
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#define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL1)
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLAT_MAX_RET_STATE U(1)
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/* Interrupt controller */
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#define POPLAR_GICD_BASE GICD_BASE
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#define POPLAR_GICC_BASE GICC_BASE
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#define POPLAR_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(HISI_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_TIMER0, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_TIMER1, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_TIMER2, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_TIMER3, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(HISI_IRQ_SEC_AXI, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL)
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#define POPLAR_G0_IRQ_PROPS(grp)
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#endif /* PLATFORM_DEF_H */
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