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b7c6529c41
This is used as a table index, and already compared with an unsigned int: block_dev_count. Signed-off-by: Yann Gautier <yann.gautier@st.com>
84 lines
2.3 KiB
C
84 lines
2.3 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <common_def.h>
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#include <hikey_def.h>
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#include <hikey_layout.h> /* BL memory region sizes, etc */
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#include <tbbr_img_def.h>
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#include <utils_def.h>
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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/*
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* Generic platform constants
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*/
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/* Size of cacheable stacks */
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#define PLATFORM_STACK_SIZE 0x1000
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#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
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#define PLATFORM_CACHE_LINE_SIZE 64
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#define PLATFORM_CLUSTER_COUNT 2
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#define PLATFORM_CORE_COUNT_PER_CLUSTER 4
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
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PLATFORM_CORE_COUNT_PER_CLUSTER)
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#define PLAT_MAX_PWR_LVL (MPIDR_AFFLVL2)
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
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PLATFORM_CLUSTER_COUNT + 1)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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/* eMMC RPMB and eMMC User Data */
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#define MAX_IO_BLOCK_DEVICES U(2)
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/* GIC related constants (no GICR in GIC-400) */
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#define PLAT_ARM_GICD_BASE 0xF6801000
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#define PLAT_ARM_GICC_BASE 0xF6802000
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#define PLAT_ARM_GICH_BASE 0xF6804000
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#define PLAT_ARM_GICV_BASE 0xF6806000
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/*
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* Platform specific page table and MMU setup constants
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*/
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#if defined(IMAGE_BL1) || defined(IMAGE_BL32)
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#define MAX_XLAT_TABLES 3
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#endif
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#ifdef IMAGE_BL31
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#define MAX_XLAT_TABLES 4
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#endif
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#ifdef IMAGE_BL2
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#define MAX_XLAT_TABLES 4
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#endif
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#define MAX_MMAP_REGIONS 16
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/*
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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*/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#endif /* PLATFORM_DEF_H */
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