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https://github.com/ARM-software/arm-trusted-firmware.git
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ce21a1a909
DDR and IOSSM driver code for Agilex5 platform, initialize the DDR/IOSSM in BL2 EL3 early flow. Change-Id: I3e4205171d9356190b60498cae322318520bb1c2 Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
190 lines
5.3 KiB
C
190 lines
5.3 KiB
C
/*
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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* Copyright (c) 2024, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef HANDOFF_H
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#define HANDOFF_H
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#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */
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#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */
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#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */
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#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */
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#define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */
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#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */
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#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */
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#define HANDOFF_MAGIC_PERIPHERAL 0x50455249 /* PERIPHERAL */
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#define HANDOFF_MAGIC_DDR 0x5344524d /* DDR */
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#include <socfpga_plat_def.h>
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typedef struct handoff_t {
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/* header */
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uint32_t header_magic;
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uint32_t header_device;
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uint32_t _pad_0x08_0x10[2];
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/* pinmux configuration - select */
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uint32_t pinmux_sel_magic;
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uint32_t pinmux_sel_length;
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uint32_t _pad_0x18_0x20[2];
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uint32_t pinmux_sel_array[96]; /* offset, value */
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/* pinmux configuration - io control */
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uint32_t pinmux_io_magic;
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uint32_t pinmux_io_length;
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uint32_t _pad_0x1a8_0x1b0[2];
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uint32_t pinmux_io_array[96]; /* offset, value */
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/* pinmux configuration - use fpga switch */
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uint32_t pinmux_fpga_magic;
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uint32_t pinmux_fpga_length;
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uint32_t _pad_0x338_0x340[2];
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uint32_t pinmux_fpga_array[44]; /* offset, value */
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/* TODO: Temp remove due to add in extra handoff data */
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// uint32_t _pad_0x3e8_0x3f0[2];
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/* pinmux configuration - io delay */
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uint32_t pinmux_delay_magic;
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uint32_t pinmux_delay_length;
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uint32_t _pad_0x3f8_0x400[2];
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uint32_t pinmux_iodelay_array[96]; /* offset, value */
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/* clock configuration */
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#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
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uint32_t clock_magic;
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uint32_t clock_length;
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uint32_t _pad_0x588_0x590[2];
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uint32_t main_pll_mpuclk;
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uint32_t main_pll_nocclk;
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uint32_t main_pll_cntr2clk;
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uint32_t main_pll_cntr3clk;
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uint32_t main_pll_cntr4clk;
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uint32_t main_pll_cntr5clk;
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uint32_t main_pll_cntr6clk;
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uint32_t main_pll_cntr7clk;
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uint32_t main_pll_cntr8clk;
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uint32_t main_pll_cntr9clk;
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uint32_t main_pll_nocdiv;
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uint32_t main_pll_pllglob;
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uint32_t main_pll_fdbck;
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uint32_t main_pll_pllc0;
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uint32_t main_pll_pllc1;
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uint32_t _pad_0x5cc_0x5d0[1];
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uint32_t per_pll_cntr2clk;
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uint32_t per_pll_cntr3clk;
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uint32_t per_pll_cntr4clk;
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uint32_t per_pll_cntr5clk;
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uint32_t per_pll_cntr6clk;
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uint32_t per_pll_cntr7clk;
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uint32_t per_pll_cntr8clk;
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uint32_t per_pll_cntr9clk;
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uint32_t per_pll_emacctl;
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uint32_t per_pll_gpiodiv;
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uint32_t per_pll_pllglob;
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uint32_t per_pll_fdbck;
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uint32_t per_pll_pllc0;
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uint32_t per_pll_pllc1;
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uint32_t hps_osc_clk_h;
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uint32_t fpga_clk_hz;
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#elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
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uint32_t clock_magic;
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uint32_t clock_length;
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uint32_t _pad_0x588_0x590[2];
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uint32_t main_pll_mpuclk;
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uint32_t main_pll_nocclk;
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uint32_t main_pll_nocdiv;
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uint32_t main_pll_pllglob;
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uint32_t main_pll_fdbck;
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uint32_t main_pll_pllc0;
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uint32_t main_pll_pllc1;
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uint32_t main_pll_pllc2;
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uint32_t main_pll_pllc3;
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uint32_t main_pll_pllm;
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uint32_t per_pll_emacctl;
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uint32_t per_pll_gpiodiv;
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uint32_t per_pll_pllglob;
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uint32_t per_pll_fdbck;
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uint32_t per_pll_pllc0;
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uint32_t per_pll_pllc1;
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uint32_t per_pll_pllc2;
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uint32_t per_pll_pllc3;
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uint32_t per_pll_pllm;
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uint32_t alt_emacactr;
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uint32_t alt_emacbctr;
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uint32_t alt_emacptpctr;
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uint32_t alt_gpiodbctr;
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uint32_t alt_sdmmcctr;
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uint32_t alt_s2fuser0ctr;
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uint32_t alt_s2fuser1ctr;
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uint32_t alt_psirefctr;
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uint32_t hps_osc_clk_h;
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uint32_t fpga_clk_hz;
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uint32_t _pad_0x604_0x610[3];
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#elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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uint32_t clock_magic;
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uint32_t clock_length;
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uint32_t _pad_0x588_0x590[2];
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uint32_t main_pll_nocclk;
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uint32_t main_pll_nocdiv;
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uint32_t main_pll_pllglob;
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uint32_t main_pll_fdbck;
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uint32_t main_pll_pllc0;
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uint32_t main_pll_pllc1;
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uint32_t main_pll_pllc2;
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uint32_t main_pll_pllc3;
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uint32_t main_pll_pllm;
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uint32_t per_pll_emacctl;
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uint32_t per_pll_gpiodiv;
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uint32_t per_pll_pllglob;
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uint32_t per_pll_fdbck;
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uint32_t per_pll_pllc0;
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uint32_t per_pll_pllc1;
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uint32_t per_pll_pllc2;
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uint32_t per_pll_pllc3;
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uint32_t per_pll_pllm;
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uint32_t alt_emacactr;
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uint32_t alt_emacbctr;
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uint32_t alt_emacptpctr;
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uint32_t alt_gpiodbctr;
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uint32_t alt_sdmmcctr;
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uint32_t alt_s2fuser0ctr;
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uint32_t alt_s2fuser1ctr;
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uint32_t alt_psirefctr;
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/* TODO: Temp added for clk manager. */
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uint32_t qspi_clk_khz;
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uint32_t hps_osc_clk_hz;
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uint32_t fpga_clk_hz;
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/* TODO: Temp added for clk manager. */
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uint32_t ddr_reset_type;
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/* TODO: Temp added for clk manager. */
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uint32_t hps_status_coldreset;
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/* TODO: Temp remove due to add in extra handoff data */
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//uint32_t _pad_0x604_0x610[3];
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#endif
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/* misc configuration */
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uint32_t misc_magic;
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uint32_t misc_length;
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uint32_t _pad_0x618_0x620[2];
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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/* peripheral configuration - select */
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uint32_t peripheral_pwr_gate_magic;
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uint32_t peripheral_pwr_gate_length;
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uint32_t _pad_0x08_0x0C[2];
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uint32_t peripheral_pwr_gate_array; /* offset, value */
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/* ddr configuration - select */
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uint32_t ddr_magic;
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uint32_t ddr_length;
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uint32_t _pad_0x1C_0x20[2];
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uint32_t ddr_config; /* BIT[0]-Dual Port. BIT[1]-Dual EMIF */
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#endif
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} handoff;
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int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr);
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int socfpga_get_handoff(handoff *hoff_ptr);
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#endif
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