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https://github.com/ARM-software/arm-trusted-firmware.git
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bd9344f670
Use full include paths like it is done for common includes.
This cleanup was started in commit d40e0e08283a ("Sanitise includes
across codebase"), but it only cleaned common files and drivers. This
patch does the same to Arm platforms.
Change-Id: If982e6450bbe84dceb56d464e282bcf5d6d9ab9b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
73 lines
2.1 KiB
C
73 lines
2.1 KiB
C
/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <drivers/arm/nic_400.h>
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#include <lib/mmio.h>
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#include <plat/arm/soc/common/soc_css.h>
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void soc_css_init_nic400(void)
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{
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/*
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* NIC-400 Access Control Initialization
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*
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* Define access privileges by setting each corresponding bit to:
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* 0 = Secure access only
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* 1 = Non-secure access allowed
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*/
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/*
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* Allow non-secure access to some SOC regions, excluding UART1, which
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* remains secure (unless CSS_NON_SECURE_UART is set).
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* Note: This is the NIC-400 device on the SOC
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*/
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mmio_write_32(SOC_CSS_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_EHCI), ~0);
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mmio_write_32(SOC_CSS_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_TLX_MASTER), ~0);
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mmio_write_32(SOC_CSS_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_OHCI), ~0);
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mmio_write_32(SOC_CSS_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_PL354_SMC), ~0);
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mmio_write_32(SOC_CSS_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_APB4_BRIDGE), ~0);
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#if CSS_NON_SECURE_UART
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/* Configure UART for non-secure access */
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mmio_write_32(SOC_CSS_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE), ~0);
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#else
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mmio_write_32(SOC_CSS_NIC400_BASE +
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NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE),
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~SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1);
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#endif /* CSS_NON_SECURE_UART */
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}
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#define PCIE_SECURE_REG 0x3000
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/* Mask uses REG and MEM access bits */
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#define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1))
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void soc_css_init_pcie(void)
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{
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#if !PLAT_juno
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/*
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* Do not initialize PCIe in emulator environment.
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* Platform ID register not supported on Juno
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*/
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if (BOARD_CSS_GET_PLAT_TYPE(BOARD_CSS_PLAT_ID_REG_ADDR) ==
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BOARD_CSS_PLAT_TYPE_EMULATOR)
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return;
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#endif /* PLAT_juno */
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/*
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* PCIE Root Complex Security settings to enable non-secure
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* access to config registers.
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*/
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mmio_write_32(SOC_CSS_PCIE_CONTROL_BASE + PCIE_SECURE_REG,
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PCIE_SEC_ACCESS_MASK);
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}
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