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b62673c645
The existing DSU errata workarounds hijack the errata framework's inner workings to register with it. However, that is undesirable as any change to the framework may end up missing these workarounds. So convert the checks and workarounds to macros and have them included with the standard wrappers. The only problem with this is the is_scu_present_in_dsu weak function. Fortunately, it is only needed for 2 of the errata and only on 3 cores. So drop it, assuming the default behaviour and have the callers handle the exception. Change-Id: Iefa36325804ea093e938f867b9a6f49a6984b8ae Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
151 lines
4.6 KiB
ArmAsm
151 lines
4.6 KiB
ArmAsm
/*
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* Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a55.h>
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#include <cpu_macros.S>
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#include <dsu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A55 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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.globl cortex_a55_reset_func
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.globl cortex_a55_core_pwr_dwn
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workaround_reset_start cortex_a55, ERRATUM(798953), ERRATA_DSU_798953
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errata_dsu_798953_wa_impl
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workaround_reset_end cortex_a55, ERRATUM(798953)
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check_erratum_custom_start cortex_a55, ERRATUM(798953)
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check_errata_dsu_798953_impl
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ret
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check_erratum_custom_end cortex_a55, ERRATUM(798953)
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workaround_reset_start cortex_a55, ERRATUM(936184), ERRATA_DSU_936184
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errata_dsu_936184_wa_impl
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workaround_reset_end cortex_a55, ERRATUM(936184)
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check_erratum_custom_start cortex_a55, ERRATUM(936184)
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check_errata_dsu_936184_impl
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ret
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check_erratum_custom_end cortex_a55, ERRATUM(936184)
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workaround_reset_start cortex_a55, ERRATUM(768277), ERRATA_A55_768277
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sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
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workaround_reset_end cortex_a55, ERRATUM(768277)
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check_erratum_ls cortex_a55, ERRATUM(768277), CPU_REV(0, 0)
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workaround_reset_start cortex_a55, ERRATUM(778703), ERRATA_A55_778703
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sysreg_bit_set CORTEX_A55_CPUECTLR_EL1, CORTEX_A55_CPUECTLR_EL1_L1WSCTL
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sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING
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workaround_reset_end cortex_a55, ERRATUM(778703)
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check_erratum_custom_start cortex_a55, ERRATUM(778703)
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mov x16, x30
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mov x1, #0x00
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bl cpu_rev_var_ls
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/*
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* Check that no private L2 cache is configured
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*/
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mrs x1, CORTEX_A55_CLIDR_EL1
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and x1, x1, CORTEX_A55_CLIDR_EL1_CTYPE3
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cmp x1, #0
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mov x2, #ERRATA_NOT_APPLIES
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csel x0, x0, x2, eq
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ret x16
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check_erratum_custom_end cortex_a55, ERRATUM(778703)
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workaround_reset_start cortex_a55, ERRATUM(798797), ERRATA_A55_798797
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sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
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workaround_reset_end cortex_a55, ERRATUM(798797)
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check_erratum_ls cortex_a55, ERRATUM(798797), CPU_REV(0, 0)
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workaround_reset_start cortex_a55, ERRATUM(846532), ERRATA_A55_846532
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sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
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workaround_reset_end cortex_a55, ERRATUM(846532)
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check_erratum_ls cortex_a55, ERRATUM(846532), CPU_REV(0, 1)
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workaround_reset_start cortex_a55, ERRATUM(903758), ERRATA_A55_903758
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sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
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workaround_reset_end cortex_a55, ERRATUM(903758)
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check_erratum_ls cortex_a55, ERRATUM(903758), CPU_REV(0, 1)
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workaround_reset_start cortex_a55, ERRATUM(1221012), ERRATA_A55_1221012
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mov x0, #0x0020
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movk x0, #0x0850, lsl #16
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msr CPUPOR_EL3, x0
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mov x0, #0x0000
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movk x0, #0x1FF0, lsl #16
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movk x0, #0x2, lsl #32
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msr CPUPMR_EL3, x0
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mov x0, #0x03fd
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movk x0, #0x0110, lsl #16
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msr CPUPCR_EL3, x0
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mov x0, #0x1
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msr CPUPSELR_EL3, x0
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mov x0, #0x0040
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movk x0, #0x08D0, lsl #16
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msr CPUPOR_EL3, x0
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mov x0, #0x0040
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movk x0, #0x1FF0, lsl #16
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movk x0, #0x2, lsl #32
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msr CPUPMR_EL3, x0
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mov x0, #0x03fd
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movk x0, #0x0110, lsl #16
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msr CPUPCR_EL3, x0
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workaround_reset_end cortex_a55, ERRATUM(1221012)
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check_erratum_ls cortex_a55, ERRATUM(1221012), CPU_REV(1, 0)
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check_erratum_chosen cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923
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/* erratum has no workaround in the cpu. Generic code must take care */
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add_erratum_entry cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923, NO_APPLY_AT_RESET
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cpu_reset_func_start cortex_a55
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cpu_reset_func_end cortex_a55
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func cortex_a55_core_pwr_dwn
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sysreg_bit_set CORTEX_A55_CPUPWRCTLR_EL1, CORTEX_A55_CORE_PWRDN_EN_MASK
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isb
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ret
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endfunc cortex_a55_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides cortex_a55 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a55_regs, "aS"
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cortex_a55_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a55_cpu_reg_dump
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adr x6, cortex_a55_regs
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mrs x8, CORTEX_A55_CPUECTLR_EL1
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ret
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endfunc cortex_a55_cpu_reg_dump
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declare_cpu_ops cortex_a55, CORTEX_A55_MIDR, \
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cortex_a55_reset_func, \
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cortex_a55_core_pwr_dwn
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