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b62673c645
The existing DSU errata workarounds hijack the errata framework's inner workings to register with it. However, that is undesirable as any change to the framework may end up missing these workarounds. So convert the checks and workarounds to macros and have them included with the standard wrappers. The only problem with this is the is_scu_present_in_dsu weak function. Fortunately, it is only needed for 2 of the errata and only on 3 cores. So drop it, assuming the default behaviour and have the callers handle the exception. Change-Id: Iefa36325804ea093e938f867b9a6f49a6984b8ae Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
62 lines
1.9 KiB
C
62 lines
1.9 KiB
C
/*
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* Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef DSU_DEF_H
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#define DSU_DEF_H
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#include <lib/utils_def.h>
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/********************************************************************
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* DSU Cluster Configuration registers definitions
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********************************************************************/
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#define CLUSTERCFR_EL1 S3_0_C15_C3_0
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#define CLUSTERCFR_ACP_SHIFT U(11)
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/********************************************************************
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* DSU Cluster Main Revision ID registers definitions
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********************************************************************/
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#define CLUSTERIDR_EL1 S3_0_C15_C3_1
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#define CLUSTERIDR_REV_SHIFT U(0)
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#define CLUSTERIDR_REV_BITS U(4)
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#define CLUSTERIDR_VAR_SHIFT U(4)
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#define CLUSTERIDR_VAR_BITS U(4)
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/********************************************************************
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* DSU Cluster Auxiliary Control registers definitions
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********************************************************************/
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#define CLUSTERACTLR_EL1 S3_0_C15_C3_3
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#define CLUSTERPWRCTLR_EL1 S3_0_C15_C3_5
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#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15)
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#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15)
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/********************************************************************
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* Masks applied for DSU errata workarounds
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********************************************************************/
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#define DSU_ERRATA_936184_MASK (U(0x3) << 15)
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#define CPUCFR_EL1 S3_0_C15_C0_0
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/* SCU bit of CPU Configuration Register, EL1 */
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#define SCU_SHIFT U(2)
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#ifndef __ASSEMBLER__
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DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrctlr_el1, CLUSTERPWRCTLR_EL1);
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/* ---------------------------------------------
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* controls power features of the cluster
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* 1. Cache portion power not request
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* 2. Disable the retention circuit
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* ---------------------------------------------
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*/
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static inline void dsu_pwr_dwn(void)
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{
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write_clusterpwrctlr_el1(0);
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isb();
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}
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#endif
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#endif /* DSU_DEF_H */
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