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29bda258d5
Cortex-X925 erratum 2963999 that applies to r0p0 and is fixed in r0p1. In EL3, reads of MPIDR_EL1 and MIDR_EL1 might incorrectly virtualize which register to return when reading the value of MPIDR_EL1/VMPIDR_EL2 and MIDR_EL1/VPIDR_EL2, respectively. The workaround is to do an ISB prior to an MRS read to either MPIDR_EL1 and MIDR_EL1. SDEN documentation: https://developer.arm.com/documentation/109180/latest/ Change-Id: I447fd359ea32e1d274e1245886e1de57d14f082c Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
107 lines
3.4 KiB
ArmAsm
107 lines
3.4 KiB
ArmAsm
/*
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* Copyright (c) 2023-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_x925.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-X925 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-X925 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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.global check_erratum_cortex_x925_3701747
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add_erratum_entry cortex_x925, ERRATUM(3701747), ERRATA_X925_3701747, NO_APPLY_AT_RESET
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check_erratum_ls cortex_x925, ERRATUM(3701747), CPU_REV(0, 1)
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workaround_reset_start cortex_x925, ERRATUM(2963999), ERRATA_X925_2963999
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/* Add ISB before MRS reads of MPIDR_EL1/MIDR_EL1 */
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ldr x0, =0x0
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msr S3_6_c15_c8_0, x0 /* msr CPUPSELR_EL3, X0 */
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ldr x0, =0xd5380000
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msr S3_6_c15_c8_2, x0 /* msr CPUPOR_EL3, X0 */
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ldr x0, =0xFFFFFF40
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msr S3_6_c15_c8_3,x0 /* msr CPUPMR_EL3, X0 */
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ldr x0, =0x000080010033f
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msr S3_6_c15_c8_1, x0 /* msr CPUPCR_EL3, X0 */
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isb
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workaround_reset_end cortex_x925, ERRATUM(2963999)
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check_erratum_ls cortex_x925, ERRATUM(2963999), CPU_REV(0, 0)
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_x925, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_X925_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_x925, CVE(2024, 5660)
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check_erratum_ls cortex_x925, CVE(2024, 5660), CPU_REV(0, 1)
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workaround_reset_start cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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/* ---------------------------------
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* Sets BIT41 of CPUACTLR6_EL1 which
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* disables L1 Data cache prefetcher
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* ---------------------------------
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*/
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sysreg_bit_set CORTEX_X925_CPUACTLR6_EL1, BIT(41)
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workaround_reset_end cortex_x925, CVE(2024, 7881)
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check_erratum_chosen cortex_x925, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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cpu_reset_func_start cortex_x925
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/* Disable speculative loads */
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msr SSBS, xzr
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cpu_reset_func_end cortex_x925
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_x925_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set CORTEX_X925_CPUPWRCTLR_EL1, CORTEX_X925_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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isb
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ret
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endfunc cortex_x925_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides Cortex-X925 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_x925_regs, "aS"
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cortex_x925_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_x925_cpu_reg_dump
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adr x6, cortex_x925_regs
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mrs x8, CORTEX_X925_CPUECTLR_EL1
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ret
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endfunc cortex_x925_cpu_reg_dump
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declare_cpu_ops_wa_4 cortex_x925, CORTEX_X925_MIDR, \
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cortex_x925_reset_func, \
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CPU_NO_EXTRA1_FUNC, \
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CPU_NO_EXTRA2_FUNC, \
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CPU_NO_EXTRA3_FUNC, \
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check_erratum_cortex_x925_7881, \
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cortex_x925_core_pwr_dwn
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