mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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b529799ff1
synquacer uses GICv3 compliant GIC500. So enable proper GICv3 driver initialization. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
114 lines
3 KiB
C
114 lines
3 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <platform_def.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <pl011.h>
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#include <debug.h>
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#include <sq_common.h>
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static console_pl011_t console;
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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assert(sec_state_is_valid(type));
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return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info;
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}
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/*******************************************************************************
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* Gets SPSR for BL32 entry
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******************************************************************************/
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uint32_t sq_get_spsr_for_bl32_entry(void)
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{
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL32 image.
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*/
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return 0;
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}
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/*******************************************************************************
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* Gets SPSR for BL33 entry
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******************************************************************************/
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uint32_t sq_get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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unsigned int mode;
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uint32_t spsr;
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/* Figure out what mode we enter the non-secure world in */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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mode = (el_status) ? MODE_EL2 : MODE_EL1;
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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void bl31_early_platform_setup(bl31_params_t *from_bl2,
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void *plat_params_from_bl2)
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{
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/* Initialize the console to provide early debug support */
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(void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE,
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PLAT_SQ_BOOT_UART_CLK_IN_HZ,
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SQ_CONSOLE_BAUDRATE, &console);
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console_set_scope(&console.console, CONSOLE_FLAG_BOOT |
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CONSOLE_FLAG_RUNTIME);
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/* There are no parameters from BL2 if BL31 is a reset vector */
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assert(from_bl2 == NULL);
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assert(plat_params_from_bl2 == NULL);
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#ifdef BL32_BASE
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/* Populate entry point information for BL32 */
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SET_PARAM_HEAD(&bl32_image_ep_info,
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PARAM_EP,
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VERSION_1,
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0);
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SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
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bl32_image_ep_info.pc = BL32_BASE;
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bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry();
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#endif /* BL32_BASE */
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/* Populate entry point information for BL33 */
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SET_PARAM_HEAD(&bl33_image_ep_info,
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PARAM_EP,
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VERSION_1,
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0);
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/*
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* Tell BL31 where the non-trusted software image
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* is located and the entry state information
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*/
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bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
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bl33_image_ep_info.spsr = sq_get_spsr_for_bl33_entry();
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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}
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void bl31_platform_setup(void)
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{
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/* Initialize the CCN interconnect */
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plat_sq_interconnect_init();
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plat_sq_interconnect_enter_coherency();
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/* Initialize the GIC driver, cpu and distributor interfaces */
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sq_gic_driver_init();
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sq_gic_init();
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}
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void bl31_plat_runtime_setup(void)
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{
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}
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void bl31_plat_arch_setup(void)
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{
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}
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