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https://github.com/ARM-software/arm-trusted-firmware.git
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167a935733
Consolidate all BL3-1 CPU context initialization for cold boot, PSCI and SPDs into two functions: * The first uses entry_point_info to initialize the relevant cpu_context for first entry into a lower exception level on a CPU * The second populates the EL1 and EL2 system registers as needed from the cpu_context to ensure correct entry into the lower EL This patch alters the way that BL3-1 determines which exception level is used when first entering EL1 or EL2 during cold boot - this is now fully determined by the SPSR value in the entry_point_info for BL3-3, as set up by the platform code in BL2 (or otherwise provided to BL3-1). In the situation that EL1 (or svc mode) is selected for a processor that supports EL2, the context management code will now configure all essential EL2 register state to ensure correct execution of EL1. This allows the platform code to run non-secure EL1 payloads directly without requiring a small EL2 stub or OS loader. Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f
93 lines
4 KiB
C
93 lines
4 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CM_H__
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#define __CM_H__
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#include <cpu_data.h>
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#include <stdint.h>
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/*******************************************************************************
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* Forward declarations
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******************************************************************************/
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struct entry_point_info;
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/*******************************************************************************
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* Function & variable prototypes
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******************************************************************************/
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void cm_init(void);
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void *cm_get_context_by_mpidr(uint64_t mpidr, uint32_t security_state);
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static inline void *cm_get_context(uint32_t security_state);
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void cm_set_context_by_mpidr(uint64_t mpidr,
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void *context,
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uint32_t security_state);
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static inline void cm_set_context(void *context, uint32_t security_state);
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void cm_el3_sysregs_context_save(uint32_t security_state);
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void cm_init_context(uint64_t mpidr, const struct entry_point_info *ep);
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void cm_prepare_el3_exit(uint32_t security_state);
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void cm_el3_sysregs_context_restore(uint32_t security_state);
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void cm_el1_sysregs_context_save(uint32_t security_state);
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void cm_el1_sysregs_context_restore(uint32_t security_state);
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void cm_set_elr_el3(uint32_t security_state, uint64_t entrypoint);
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void cm_set_elr_spsr_el3(uint32_t security_state,
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uint64_t entrypoint, uint32_t spsr);
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void cm_write_scr_el3_bit(uint32_t security_state,
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uint32_t bit_pos,
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uint32_t value);
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void cm_set_next_eret_context(uint32_t security_state);
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uint32_t cm_get_scr_el3(uint32_t security_state);
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/* Inline definitions */
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/*******************************************************************************
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* This function returns a pointer to the most recent 'cpu_context' structure
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* for the calling CPU that was set as the context for the specified security
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* state. NULL is returned if no such structure has been specified.
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******************************************************************************/
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void *cm_get_context(uint32_t security_state)
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{
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assert(security_state <= NON_SECURE);
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return get_cpu_data(cpu_context[security_state]);
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}
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/*******************************************************************************
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* This function sets the pointer to the current 'cpu_context' structure for the
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* specified security state for the calling CPU
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******************************************************************************/
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void cm_set_context(void *context, uint32_t security_state)
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{
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assert(security_state <= NON_SECURE);
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set_cpu_data(cpu_context[security_state], context);
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}
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#endif /* __CM_H__ */
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