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a1b6db6c62
This patch re-organizes the memory layout on FVP as to give the
BL3-2 image as much memory as possible.
Considering these two facts:
- not all images need to live in memory at the same time. Once
in BL3-1, the memory used by BL1 and BL2 can be reclaimed.
- when BL2 loads the BL3-1 and BL3-2 images, it only considers the
PROGBITS sections of those 2 images. The memory occupied by the
NOBITS sections will be touched only at execution of the BL3-x
images;
Then it is possible to choose the different base addresses such that
the NOBITS sections of BL3-1 and BL3-2 overlay BL1 and BL2.
On FVP we choose to put:
- BL1 and BL3-1 at the top of the Trusted RAM, with BL3-1 NOBITS
sections overlaying BL1;
- BL3-2 at the bottom of the Trusted RAM, with its NOBITS sections
overlaying BL2;
This is illustrated by the following diagram:
0x0404_0000 ------------ ------------------
| BL1 | <= | BL3-1 NOBITS |
------------ <= ------------------
| | <= | BL3-1 PROGBITS |
------------ ------------------
| BL2 | <= | BL3-2 NOBITS |
------------ <= ------------------
| | <= | BL3-2 PROGBITS |
0x0400_0000 ------------ ------------------
New platform-specific constants have been introduced to easily check
at link time that BL3-1 and BL3-2 PROGBITS sections don't overwrite
BL1 and BL2. These are optional and the platform code is free to define
them or not. If not defined, the linker won't attempt to check
image overlaying.
Fixes ARM-software/tf-issues#117
Change-Id: I5981d1c3d66ee70eaac8bd052630c9ac6dd8b042
134 lines
4.3 KiB
ArmAsm
134 lines
4.3 KiB
ArmAsm
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <platform_def.h>
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OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
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OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
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ENTRY(bl31_entrypoint)
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MEMORY {
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RAM (rwx): ORIGIN = TZRAM_BASE, LENGTH = TZRAM_SIZE
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}
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SECTIONS
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{
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. = BL31_BASE;
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ASSERT(. == ALIGN(4096),
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"BL31_BASE address is not aligned on a page boundary.")
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ro . : {
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__RO_START__ = .;
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*bl31_entrypoint.o(.text*)
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*(.text*)
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*(.rodata*)
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/* Ensure 8-byte alignment for descriptors and ensure inclusion */
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. = ALIGN(8);
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__RT_SVC_DESCS_START__ = .;
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KEEP(*(rt_svc_descs))
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__RT_SVC_DESCS_END__ = .;
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*(.vectors)
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__RO_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked as read-only,
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* executable. No RW data from the next section must creep in.
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* Ensure the rest of the current memory page is unused.
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*/
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. = NEXT(4096);
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__RO_END__ = .;
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} >RAM
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.data . : {
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__DATA_START__ = .;
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*(.data*)
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__DATA_END__ = .;
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} >RAM
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#ifdef BL31_PROGBITS_LIMIT
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ASSERT(. <= BL31_PROGBITS_LIMIT, "BL3-1 progbits has exceeded its limit.")
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#endif
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stacks (NOLOAD) : {
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__STACKS_START__ = .;
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*(tzfw_normal_stacks)
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__STACKS_END__ = .;
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} >RAM
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/*
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* The .bss section gets initialised to 0 at runtime.
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* Its base address must be 16-byte aligned.
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*/
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.bss : ALIGN(16) {
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__BSS_START__ = .;
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*(.bss*)
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*(COMMON)
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__BSS_END__ = .;
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} >RAM
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/*
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* The xlat_table section is for full, aligned page tables (4K).
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* Removing them from .bss avoids forcing 4K alignment on
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* the .bss section and eliminates the unecessary zero init
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*/
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xlat_table (NOLOAD) : {
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*(xlat_table)
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} >RAM
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/*
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* The base address of the coherent memory section must be page-aligned (4K)
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* to guarantee that the coherent data are stored on their own pages and
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* are not mixed with normal data. This is required to set up the correct
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* memory attributes for the coherent data page tables.
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*/
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coherent_ram (NOLOAD) : ALIGN(4096) {
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__COHERENT_RAM_START__ = .;
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*(tzfw_coherent_mem)
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__COHERENT_RAM_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked
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* as device memory. No other unexpected data must creep in.
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* Ensure the rest of the current memory page is unused.
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*/
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. = NEXT(4096);
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__COHERENT_RAM_END__ = .;
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} >RAM
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__BL31_END__ = .;
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__BSS_SIZE__ = SIZEOF(.bss);
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__COHERENT_RAM_UNALIGNED_SIZE__ =
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__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
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ASSERT(. <= BL31_LIMIT, "BL3-1 image has exceeded its limit.")
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}
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