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ca661a0092
This flag warns if anything is declared more than once in the same scope, even in cases where multiple declaration is valid and changes nothing. Consequently, this patch also fixes the issues reported by this flag. Consider the following two lines of code from two different source files(bl_common.h and bl31_plat_setup.c): IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE); The IMPORT_SYM macro which actually imports a linker symbol as a C expression. The macro defines the __RO_START__ as an extern variable twice, one for each instance. __RO_START__ symbol is defined by the linker script to mark the start of the Read-Only area of the memory map. Essentially, the platform code redefines the linker symbol with a different (relevant) name rather than using the standard symbol. A simple solution to fix this issue in the platform code for redundant declarations warning is to remove the second IMPORT_SYM and replace it with following assignment static const unsigned long BL2_RO_BASE = BL_CODE_BASE; Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
129 lines
3.2 KiB
C
129 lines
3.2 KiB
C
/*
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* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stddef.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <bl31/bl31.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/arm/cci.h>
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#include <drivers/console.h>
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#include "pwrc.h"
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#include "rcar_def.h"
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#include "rcar_private.h"
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#include "rcar_version.h"
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static const uint64_t BL31_RO_BASE = BL_CODE_BASE;
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static const uint64_t BL31_RO_LIMIT = BL_CODE_END;
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#if USE_COHERENT_MEM
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static const uint64_t BL31_COHERENT_RAM_BASE = BL_COHERENT_RAM_BASE;
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static const uint64_t BL31_COHERENT_RAM_LIMIT = BL_COHERENT_RAM_END;
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#endif
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extern void plat_rcar_gic_driver_init(void);
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extern void plat_rcar_gic_init(void);
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u_register_t rcar_boot_mpidr;
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static int cci_map[] = {
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CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3,
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CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3
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};
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void plat_cci_init(void)
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{
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uint32_t prd;
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prd = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
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if (PRR_PRODUCT_H3_CUT10 == prd || PRR_PRODUCT_H3_CUT11 == prd) {
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cci_map[0U] = CCI500_CLUSTER0_SL_IFACE_IX;
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cci_map[1U] = CCI500_CLUSTER1_SL_IFACE_IX;
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}
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cci_init(RCAR_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
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}
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void plat_cci_enable(void)
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{
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
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}
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void plat_cci_disable(void)
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{
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cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
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}
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struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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bl2_to_bl31_params_mem_t *from_bl2 = (bl2_to_bl31_params_mem_t *)
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PARAMS_BASE;
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entry_point_info_t *next_image_info;
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next_image_info = (type == NON_SECURE) ?
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&from_bl2->bl33_ep_info : &from_bl2->bl32_ep_info;
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return next_image_info->pc ? next_image_info : NULL;
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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rcar_console_runtime_init();
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NOTICE("BL3-1 : Rev.%s\n", version_of_renesas);
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#if RCAR_LSI != RCAR_D3
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if (RCAR_CLUSTER_A53A57 == rcar_pwrc_get_cluster()) {
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plat_cci_init();
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plat_cci_enable();
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}
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#endif
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}
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void bl31_plat_arch_setup(void)
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{
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rcar_configure_mmu_el3(BL31_BASE,
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BL31_LIMIT - BL31_BASE,
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BL31_RO_BASE, BL31_RO_LIMIT
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#if USE_COHERENT_MEM
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, BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT
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#endif
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);
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rcar_pwrc_code_copy_to_system_ram();
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}
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void bl31_platform_setup(void)
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{
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plat_rcar_gic_driver_init();
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plat_rcar_gic_init();
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/* enable the system level generic timer */
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mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(U(0)) | CNTCR_EN);
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rcar_pwrc_setup();
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#if 0
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/* TODO: there is a broad number of rcar-gen3 SoC configurations; to
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support all of them, Renesas use the pwrc driver to discover what
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cores are on/off before announcing the topology.
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This code hasnt been ported yet
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*/
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rcar_setup_topology();
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#endif
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/* mask should match the kernel's MPIDR_HWID_BITMASK so the core can be
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identified during cpuhotplug (check the kernel's psci migrate set of
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functions */
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rcar_boot_mpidr = read_mpidr_el1() & 0x0000ffffU;
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}
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