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6a2426a94f
Enable the spm_mm framework for the qemu_sbsa platform. Memory layout required for spm_mm is created in secure SRAM. Co-developed-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I104a623e8bc1e44d035b95f014a13b3f8b33a62a
81 lines
2.5 KiB
C
81 lines
2.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2020, Linaro Limited and Contributors. All rights reserved.
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*/
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#include <bl31/ehf.h>
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#include <lib/xlat_tables/xlat_tables_compat.h>
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#include <services/spm_mm_partition.h>
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#include <platform_def.h>
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/* Region equivalent to MAP_DEVICE1 suitable for mapping at EL0 */
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#define MAP_DEVICE1_EL0 MAP_REGION_FLAT(DEVICE1_BASE, \
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DEVICE1_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
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const mmap_region_t plat_qemu_secure_partition_mmap[] = {
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MAP_DEVICE1_EL0, /* for the UART */
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QEMU_SP_IMAGE_MMAP,
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QEMU_SPM_BUF_EL0_MMAP,
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QEMU_SP_IMAGE_NS_BUF_MMAP,
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QEMU_SP_IMAGE_RW_MMAP,
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{0}
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};
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/*
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* Boot information passed to a secure partition during initialisation.
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* Linear indices in MP information will be filled at runtime.
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*/
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static spm_mm_mp_info_t sp_mp_info[] = {
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[0] = {0x80000000, 0},
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[1] = {0x80000001, 0},
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[2] = {0x80000002, 0},
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[3] = {0x80000003, 0},
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[4] = {0x80000004, 0},
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[5] = {0x80000005, 0},
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[6] = {0x80000006, 0},
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[7] = {0x80000007, 0}
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};
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const spm_mm_boot_info_t plat_qemu_secure_partition_boot_info = {
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.h.type = PARAM_SP_IMAGE_BOOT_INFO,
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.h.version = VERSION_1,
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.h.size = sizeof(spm_mm_boot_info_t),
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.h.attr = 0,
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.sp_mem_base = PLAT_QEMU_SP_IMAGE_BASE,
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.sp_mem_limit = BL32_LIMIT,
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.sp_image_base = PLAT_QEMU_SP_IMAGE_BASE,
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.sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
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.sp_heap_base = PLAT_QEMU_SP_IMAGE_HEAP_BASE,
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.sp_ns_comm_buf_base = PLAT_QEMU_SP_IMAGE_NS_BUF_BASE,
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.sp_shared_buf_base = PLAT_SPM_BUF_BASE,
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.sp_image_size = PLAT_QEMU_SP_IMAGE_SIZE,
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.sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
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.sp_heap_size = PLAT_QEMU_SP_IMAGE_HEAP_SIZE,
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.sp_ns_comm_buf_size = PLAT_QEMU_SP_IMAGE_NS_BUF_SIZE,
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.sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
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.num_sp_mem_regions = PLAT_QEMU_SP_IMAGE_NUM_MEM_REGIONS,
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.num_cpus = PLATFORM_CORE_COUNT,
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.mp_info = sp_mp_info
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};
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/* Enumeration of priority levels on QEMU platforms. */
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ehf_pri_desc_t qemu_exceptions[] = {
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EHF_PRI_DESC(QEMU_PRI_BITS, PLAT_SP_PRI)
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};
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/* Plug in QEMU exceptions to Exception Handling Framework. */
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EHF_REGISTER_PRIORITIES(qemu_exceptions, ARRAY_SIZE(qemu_exceptions),
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QEMU_PRI_BITS);
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const mmap_region_t *plat_get_secure_partition_mmap(void *cookie)
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{
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return plat_qemu_secure_partition_mmap;
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}
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const spm_mm_boot_info_t *
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plat_get_secure_partition_boot_info(void *cookie)
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{
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return &plat_qemu_secure_partition_boot_info;
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}
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