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506ffe50de
The non-secure world has no business accessing the CPU power switches in the PRCM; those are handled by TF-A or the SCP. Only allow access to the clock control part of the PRCM. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I657b97f4ea8a0073448ad3343fbc66ba168ed89e
47 lines
1.3 KiB
C
47 lines
1.3 KiB
C
/*
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <sunxi_mmap.h>
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#include <sunxi_private.h>
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#ifdef SUNXI_SPC_BASE
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#define SPC_DECPORT_STA_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0x4)
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#define SPC_DECPORT_SET_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0x8)
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#define SPC_DECPORT_CLR_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0xc)
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#endif
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#define R_PRCM_SEC_SWITCH_REG 0x1d0
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#define DMA_SEC_REG 0x20
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/*
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* Setup the peripherals to be accessible by non-secure world.
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* This will not work for the Secure Peripherals Controller (SPC) unless
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* a fuse it burnt (seems to be an erratum), but we do it nevertheless,
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* to allow booting on boards using secure boot.
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*/
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void sunxi_security_setup(void)
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{
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#ifdef SUNXI_SPC_BASE
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int i;
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INFO("Configuring SPC Controller\n");
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/* SPC setup: set all devices to non-secure */
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for (i = 0; i < 6; i++)
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mmio_write_32(SPC_DECPORT_SET_REG(i), 0xff);
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#endif
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/* set MBUS clocks, bus clocks (AXI/AHB/APB) and PLLs to non-secure */
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mmio_write_32(SUNXI_CCU_SEC_SWITCH_REG, 0x7);
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/* Set R_PRCM bus clocks to non-secure */
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mmio_write_32(SUNXI_R_PRCM_BASE + R_PRCM_SEC_SWITCH_REG, 0x1);
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/* Set all DMA channels (16 max.) to non-secure */
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mmio_write_32(SUNXI_DMA_BASE + DMA_SEC_REG, 0xffff);
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}
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