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12af5ed4fb
Previously the errata reporting was optional for CPU operation files and this was achieved by making use of weak reference to resolve to 0 if the symbol is not defined. This is error prone when adding new CPU operation files and weak references are problematic when fixing up dynamic relocations. Hence this patch removes the weak reference and makes it mandatory for the CPU operation files to define the errata reporting function. Change-Id: I8af192e19b85b7cd8c7579e52f8f05a4294e5396 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
84 lines
1.5 KiB
ArmAsm
84 lines
1.5 KiB
ArmAsm
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cortex_a7.h>
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#include <cpu_macros.S>
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.macro assert_cache_enabled
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#if ENABLE_ASSERTIONS
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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.endm
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func cortex_a7_disable_smp
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ldcopr r0, ACTLR
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bic r0, #CORTEX_A7_ACTLR_SMP_BIT
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stcopr r0, ACTLR
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isb
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dsb sy
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bx lr
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endfunc cortex_a7_disable_smp
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func cortex_a7_enable_smp
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ldcopr r0, ACTLR
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orr r0, #CORTEX_A7_ACTLR_SMP_BIT
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stcopr r0, ACTLR
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isb
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bx lr
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endfunc cortex_a7_enable_smp
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func cortex_a7_reset_func
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b cortex_a7_enable_smp
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endfunc cortex_a7_reset_func
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func cortex_a7_core_pwr_dwn
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push {r12, lr}
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assert_cache_enabled
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/* Flush L1 cache */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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/* Exit cluster coherency */
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pop {r12, lr}
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b cortex_a7_disable_smp
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endfunc cortex_a7_core_pwr_dwn
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func cortex_a7_cluster_pwr_dwn
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push {r12, lr}
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assert_cache_enabled
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/* Flush L1 caches */
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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bl plat_disable_acp
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/* Exit cluster coherency */
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pop {r12, lr}
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b cortex_a7_disable_smp
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endfunc cortex_a7_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex-A7. Must follow AAPCS.
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*/
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func cortex_a7_errata_report
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bx lr
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endfunc cortex_a7_errata_report
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#endif
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declare_cpu_ops cortex_a7, CORTEX_A7_MIDR, \
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cortex_a7_reset_func, \
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cortex_a7_core_pwr_dwn, \
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cortex_a7_cluster_pwr_dwn
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