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5f2c690d0e
This erratum can only be worked around on revisions >= r3p0 because the register that needs to be accessed only exists in those revisions[1]. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
30 lines
1.1 KiB
C
30 lines
1.1 KiB
C
/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A15_H
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#define CORTEX_A15_H
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#include <lib/utils_def.h>
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/*******************************************************************************
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* Auxiliary Control Register 2 specific definitions.
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******************************************************************************/
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#define CORTEX_A15_ACTLR2 p15, 1, c15, c0, 4
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#define CORTEX_A15_ACTLR2_INV_DCC_BIT (U(1) << 0)
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/*******************************************************************************
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* Cortex-A15 midr with version/revision set to 0
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******************************************************************************/
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#define CORTEX_A15_MIDR U(0x410FC0F0)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A15_ACTLR_INV_BTB_BIT (U(1) << 0)
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#define CORTEX_A15_ACTLR_SMP_BIT (U(1) << 6)
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#endif /* CORTEX_A15_H */
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