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3905f57134
Enable/Disable FPGA interfaces based on handoff configuration. Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: I8667f362aa53e7c68723e0dbd5284844ae39dfb5
35 lines
1.2 KiB
C
35 lines
1.2 KiB
C
/*
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* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef AGX_PINMUX_H
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#define AGX_PINMUX_H
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#define AGX_PINMUX_BASE 0xffd13000
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#define AGX_PINMUX_PIN0SEL (AGX_PINMUX_BASE + 0x000)
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#define AGX_PINMUX_IO0CTRL (AGX_PINMUX_BASE + 0x130)
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#define AGX_PINMUX_EMAC0_USEFPGA (AGX_PINMUX_BASE + 0x300)
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#define AGX_PINMUX_EMAC1_USEFPGA (AGX_PINMUX_BASE + 0x304)
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#define AGX_PINMUX_EMAC2_USEFPGA (AGX_PINMUX_BASE + 0x308)
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#define AGX_PINMUX_NAND_USEFPGA (AGX_PINMUX_BASE + 0x320)
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#define AGX_PINMUX_SPIM0_USEFPGA (AGX_PINMUX_BASE + 0x328)
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#define AGX_PINMUX_SPIM1_USEFPGA (AGX_PINMUX_BASE + 0x32c)
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#define AGX_PINMUX_SDMMC_USEFPGA (AGX_PINMUX_BASE + 0x354)
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#define AGX_PINMUX_IO0_DELAY (AGX_PINMUX_BASE + 0x400)
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#define AGX_PINMUX_NAND_USEFPGA_VAL BIT(4)
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#define AGX_PINMUX_SDMMC_USEFPGA_VAL BIT(8)
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#define AGX_PINMUX_SPIM0_USEFPGA_VAL BIT(16)
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#define AGX_PINMUX_SPIM1_USEFPGA_VAL BIT(24)
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#define AGX_PINMUX_EMAC0_USEFPGA_VAL BIT(0)
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#define AGX_PINMUX_EMAC1_USEFPGA_VAL BIT(8)
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#define AGX_PINMUX_EMAC2_USEFPGA_VAL BIT(16)
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#include "socfpga_handoff.h"
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void config_pinmux(handoff *handoff);
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#endif
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