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https://github.com/ARM-software/arm-trusted-firmware.git
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2368d7b157
Add the basic boot support for i.MX93. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I48bac2fd8bf2145133edf101a315908266c3f50a
63 lines
1.7 KiB
C
63 lines
1.7 KiB
C
/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdbool.h>
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#include <platform_def.h>
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#include <pwr_ctrl.h>
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/*Do the necessary GPC, SRC, BLK_CTRL_S init */
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void pwr_sys_init(void)
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{
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unsigned int cpu;
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/*
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* Assigned A55 cluster to 3, m33 to 2, A55 CORE0 & CORE1 to 0/1.
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* domain0/1 only used for trigger LPM of themselves. A55 cluster & M33's
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* domain assignment should be align with the TRDC DID.
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*/
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gpc_assign_domains(0x3102);
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/* CA55 core0/1 config */
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for (cpu = CPU_A55C0; cpu <= CPU_A55_PLAT; cpu++) {
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/* clear the cpu sleep hold */
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gpc_clear_cpu_sleep_hold(cpu);
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/* use gic wakeup source by default */
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gpc_select_wakeup_gic(cpu);
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/*
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* Ignore A55 core0/1's LPM trigger for system sleep.
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* normally, for A55 side, only the A55 cluster(plat)
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* domain will be used to trigger the system wide low
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* power mode transition.
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*/
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if (cpu != CPU_A55_PLAT) {
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gpc_force_cpu_suspend(cpu);
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}
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}
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/* boot core(A55C0) */
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src_mem_lpm_en(SRC_A55P0_MEM, MEM_OFF);
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/* For A55 core, only need to be on in RUN mode */
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src_mix_set_lpm(SRC_A55C0, 0x0, CM_MODE_WAIT);
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/* whitelist: 0x1 for domain 0 only */
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src_authen_config(SRC_A55C0, 0x1, 0x1);
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/* A55 cluster */
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gpc_select_wakeup_gic(CPU_A55_PLAT);
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gpc_clear_cpu_sleep_hold(CPU_A55_PLAT);
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/* SCU MEM must be OFF when A55 PLAT OFF */
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src_mem_lpm_en(SRC_A55_SCU_MEM, MEM_OFF);
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/* L3 memory in retention by default */
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src_mem_lpm_en(SRC_A55_L3_MEM, MEM_RETN);
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src_mix_set_lpm(SRC_A55P, 0x3, 0x1);
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/* whitelist: 0x8 for domain 3 only */
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src_authen_config(SRC_A55P, 0x8, 0x1);
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/* enable the HW LP handshake between S401 & A55 cluster */
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mmio_setbits_32(BLK_CTRL_S_BASE + HW_LP_HANDHSK, BIT(5));
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}
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