mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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278b0885eb
* changes: feat(imx8mp): optionally take params from BL2 feat(imx8mn): optionally take params from BL2 feat(imx8mm): optionally take params from BL2 feat(imx93): optionally take params from BL2 feat(imx): add helper to take params from BL2
159 lines
4.1 KiB
C
159 lines
4.1 KiB
C
/*
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* Copyright 2022-2023 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <context.h>
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#include <drivers/console.h>
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#include <drivers/generic_delay_timer.h>
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#include <drivers/nxp/trdc/imx_trdc.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <imx8_lpuart.h>
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#include <plat_common.h>
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#include <plat_imx8.h>
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#include <platform_def.h>
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#define MAP_BL31_TOTAL \
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MAP_REGION_FLAT(BL31_BASE, BL31_LIMIT - BL31_BASE, MT_MEMORY | MT_RW | MT_SECURE)
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#define MAP_BL31_RO \
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MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE)
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static const mmap_region_t imx_mmap[] = {
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AIPS1_MAP, AIPS2_MAP, AIPS4_MAP, GIC_MAP,
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TRDC_A_MAP, TRDC_W_MAP, TRDC_M_MAP,
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TRDC_N_MAP,
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{0},
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};
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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/* get SPSR for BL33 entry */
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static uint32_t get_spsr_for_bl33_entry(void)
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{
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unsigned long el_status;
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unsigned long mode;
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uint32_t spsr;
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/* figure out what mode we enter the non-secure world */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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mode = (el_status) ? MODE_EL2 : MODE_EL1;
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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static console_t console;
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console_lpuart_register(IMX_LPUART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
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IMX_CONSOLE_BAUDRATE, &console);
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/* This console is only used for boot stage */
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console_set_scope(&console, CONSOLE_FLAG_BOOT);
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/*
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* tell BL3-1 where the non-secure software image is located
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* and the entry state information.
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*/
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bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
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bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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#if defined(SPD_opteed)
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/* Populate entry point information for BL32 */
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SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
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SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
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bl32_image_ep_info.pc = BL32_BASE;
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bl32_image_ep_info.spsr = 0;
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/* Pass TEE base and size to bl33 */
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bl33_image_ep_info.args.arg1 = BL32_BASE;
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bl33_image_ep_info.args.arg2 = BL32_SIZE;
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/* Make sure memory is clean */
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mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0);
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bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
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bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
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#endif
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imx_bl31_params_parse(arg0, OCRAM_BASE, OCRAM_SIZE,
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&bl32_image_ep_info, &bl33_image_ep_info);
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}
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void bl31_plat_arch_setup(void)
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{
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/* no coherence memory support on i.MX9 */
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const mmap_region_t bl_regions[] = {
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MAP_BL31_TOTAL,
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MAP_BL31_RO,
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};
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/* Assign all the GPIO pins to non-secure world by default */
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mmio_write_32(GPIO2_BASE + 0x10, 0xffffffff);
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mmio_write_32(GPIO2_BASE + 0x14, 0x3);
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mmio_write_32(GPIO2_BASE + 0x18, 0xffffffff);
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mmio_write_32(GPIO2_BASE + 0x1c, 0x3);
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mmio_write_32(GPIO3_BASE + 0x10, 0xffffffff);
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mmio_write_32(GPIO3_BASE + 0x14, 0x3);
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mmio_write_32(GPIO3_BASE + 0x18, 0xffffffff);
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mmio_write_32(GPIO3_BASE + 0x1c, 0x3);
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mmio_write_32(GPIO4_BASE + 0x10, 0xffffffff);
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mmio_write_32(GPIO4_BASE + 0x14, 0x3);
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mmio_write_32(GPIO4_BASE + 0x18, 0xffffffff);
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mmio_write_32(GPIO4_BASE + 0x1c, 0x3);
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mmio_write_32(GPIO1_BASE + 0x10, 0xffffffff);
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mmio_write_32(GPIO1_BASE + 0x14, 0x3);
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mmio_write_32(GPIO1_BASE + 0x18, 0xffffffff);
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mmio_write_32(GPIO1_BASE + 0x1c, 0x3);
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setup_page_tables(bl_regions, imx_mmap);
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enable_mmu_el3(0);
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/* trdc must be initialized */
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trdc_config();
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}
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void bl31_platform_setup(void)
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{
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generic_delay_timer_init();
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plat_gic_driver_init();
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plat_gic_init();
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}
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entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
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{
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if (type == NON_SECURE) {
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return &bl33_image_ep_info;
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}
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if (type == SECURE) {
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return &bl32_image_ep_info;
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}
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return NULL;
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return COUNTER_FREQUENCY;
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}
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