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b495791ba2
This patch adds capability to read the boot flag to enable L2 ECC and Parity Protection bit for the Cortex-A57 CPUs. The previous bootloader sets this flag value for the platform. * with some coverity fix: MISRA C-2012 Directive 4.6 MISRA C-2012 Rule 2.5 MISRA C-2012 Rule 10.3 MISRA C-2012 Rule 10.4 Change-Id: Id7303bbbdc290b52919356c31625847b8904b073 Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
100 lines
4 KiB
ReStructuredText
100 lines
4 KiB
ReStructuredText
Tegra SoCs - Overview
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=====================
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- .. rubric:: T210
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:name: t210
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T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a
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companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores
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support Armv8-A, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
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including legacy Armv7-A applications. The Cortex-A57 processors each have
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48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared
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Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction
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and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache.
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- .. rubric:: T132
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:name: t132
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Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is
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fully Armv8-A architecture compatible. Each of the two Denver cores
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implements a 7-way superscalar microarchitecture (up to 7 concurrent
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micro-ops can be executed per clock), and includes a 128KB 4-way L1
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instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2
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cache, which services both cores.
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Denver implements an innovative process called Dynamic Code Optimization,
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which optimizes frequently used software routines at runtime into dense,
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highly tuned microcode-equivalent routines. These are stored in a
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dedicated, 128MB main-memory-based optimization cache. After being read
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into the instruction cache, the optimized micro-ops are executed,
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re-fetched and executed from the instruction cache as long as needed and
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capacity allows.
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Effectively, this reduces the need to re-optimize the software routines.
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Instead of using hardware to extract the instruction-level parallelism
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(ILP) inherent in the code, Denver extracts the ILP once via software
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techniques, and then executes those routines repeatedly, thus amortizing
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the cost of ILP extraction over the many execution instances.
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Denver also features new low latency power-state transitions, in addition
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to extensive power-gating and dynamic voltage and clock scaling based on
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workloads.
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Directory structure
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===================
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- plat/nvidia/tegra/common - Common code for all Tegra SoCs
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- plat/nvidia/tegra/soc/txxx - Chip specific code
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Trusted OS dispatcher
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=====================
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Tegra supports multiple Trusted OS', Trusted Little Kernel (TLK) being one of
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them. In order to include the 'tlkd' dispatcher in the image, pass 'SPD=tlkd'
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on the command line while preparing a bl31 image. This allows other Trusted OS
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vendors to use the upstream code and include their dispatchers in the image
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without changing any makefiles.
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Preparing the BL31 image to run on Tegra SoCs
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=============================================
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.. code:: shell
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CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
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TARGET_SOC=<target-soc e.g. t210|t132> SPD=<dispatcher e.g. tlkd> bl31
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Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=<value>``
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to the build command line.
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The Tegra platform code expects a pointer to the following platform specific
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structure via 'x1' register from the BL2 layer which is used by the
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bl31\_early\_platform\_setup() handler to extract the TZDRAM carveout base and
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size for loading the Trusted OS and the UART port ID to be used. The Tegra
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memory controller driver programs this base/size in order to restrict NS
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accesses.
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typedef struct plat\_params\_from\_bl2 {
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/\* TZ memory size */
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uint64\_t tzdram\_size;
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/* TZ memory base */
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uint64\_t tzdram\_base;
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/* UART port ID \*/
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int uart\_id;
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/* L2 ECC parity protection disable flag \*/
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int l2\_ecc\_parity\_prot\_dis;
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} plat\_params\_from\_bl2\_t;
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Power Management
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================
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The PSCI implementation expects each platform to expose the 'power state'
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parameter to be used during the 'SYSTEM SUSPEND' call. The state-id field
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is implementation defined on Tegra SoCs and is preferably defined by
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tegra\_def.h.
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Tegra configs
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=============
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- 'tegra\_enable\_l2\_ecc\_parity\_prot': This flag enables the L2 ECC and Parity
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Protection bit, for Arm Cortex-A57 CPUs, during CPU boot. This flag will
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be enabled by Tegrs SoCs during 'Cluster power up' or 'System Suspend' exit.
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