Sona Mathew af65cbb954 fix(cpus): workaround for CVE-2024-5660 for Cortex-X4 ... Implements mitigation for CVE-2024-5660 that affects Cortex-X4 revisions r0p0, r0p1, r0p2. The workaround is to disable the hardware page aggregation at EL3 by setting CPUECTLR_EL1[46] = 1'b1. Public Documentation: https://developer.arm.com/Arm%20Security%20Center/Arm%20CPU%20Vulnerability%20CVE-2024-5660 Change-Id: I378cb4978919cced03e7febc2ad431c572eac72d Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>		2024-12-17 10:24:33 -06:00
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alt-boot-flows.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
auth-framework.rst	docs(auth): extrapolate on the functions within a CM	2024-12-09 14:00:33 +00:00
cpu-specific-build-macros.rst	fix(cpus): workaround for CVE-2024-5660 for Cortex-X4	2024-12-17 10:24:33 -06:00
firmware-design.rst	refactor(mte): remove mte, mte_perm	2024-03-26 14:30:58 -05:00
index.rst	docs: add top level section numbering	2022-11-16 14:06:48 +00:00
interrupt-framework-design.rst	Fix broken links to various sections across docs	2020-08-03 09:55:04 -05:00
psci-pd-tree.rst	doc: Set correct syntax highlighting style	2019-05-22 11:28:17 +01:00
reset-design.rst	docs: update RESET_TO_BL31 documentation	2023-03-09 14:42:49 +00:00
trusted-board-boot-build.rst	docs(arm): add ARM_ROTPK_LOCATION variant full key	2022-12-09 14:55:39 -06:00
trusted-board-boot.rst	docs(auth): align TBBR CoT names to match the code	2024-02-26 12:39:06 +00:00