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464ce2bbaa
This patch adds a driver for ARM GICv2 systems, example GIC-400. Unlike the existing GIC driver in `include/drivers/arm/arm_gic.h`, this driver is optimised for GICv2 and does not support GICv3 systems in GICv2 compatibility mode. The driver interface has been implemented in `drivers/arm/gic/v2/gicv2_main.c`. The corresponding header is in `include/drivers/arm/gicv2.h`. Helper functions are implemented in `drivers/arm/gic/v2/gicv2_helpers.c` and are accessible through the `drivers/arm/gic/v2/gicv2_private.h` header. Change-Id: I09fffa4e621fb99ba3c01204839894816cd89a2a
165 lines
5.9 KiB
C
165 lines
5.9 KiB
C
/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __GICV2_H__
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#define __GICV2_H__
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/*******************************************************************************
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* GICv2 miscellaneous definitions
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******************************************************************************/
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/* Interrupt IDs reported by the HPPIR and IAR registers */
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#define PENDING_G1_INTID 1022
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/*******************************************************************************
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* GICv2 specific Distributor interface register offsets and constants.
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******************************************************************************/
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#define GICD_ITARGETSR 0x800
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#define GICD_SGIR 0xF00
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#define GICD_CPENDSGIR 0xF10
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#define GICD_SPENDSGIR 0xF20
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#define GICD_PIDR2_GICV2 0xFE8
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#define ITARGETSR_SHIFT 2
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#define GIC_TARGET_CPU_MASK 0xff
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#define CPENDSGIR_SHIFT 2
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#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT
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/*******************************************************************************
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* GICv2 specific CPU interface register offsets and constants.
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******************************************************************************/
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/* Physical CPU Interface registers */
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#define GICC_CTLR 0x0
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#define GICC_PMR 0x4
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#define GICC_BPR 0x8
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#define GICC_IAR 0xC
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#define GICC_EOIR 0x10
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#define GICC_RPR 0x14
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#define GICC_HPPIR 0x18
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#define GICC_AHPPIR 0x28
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#define GICC_IIDR 0xFC
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#define GICC_DIR 0x1000
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#define GICC_PRIODROP GICC_EOIR
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/* GICC_CTLR bit definitions */
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#define EOI_MODE_NS (1 << 10)
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#define EOI_MODE_S (1 << 9)
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#define IRQ_BYP_DIS_GRP1 (1 << 8)
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#define FIQ_BYP_DIS_GRP1 (1 << 7)
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#define IRQ_BYP_DIS_GRP0 (1 << 6)
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#define FIQ_BYP_DIS_GRP0 (1 << 5)
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#define CBPR (1 << 4)
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#define FIQ_EN_SHIFT 3
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#define FIQ_EN_BIT (1 << FIQ_EN_SHIFT)
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#define ACK_CTL (1 << 2)
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/* GICC_IIDR bit masks and shifts */
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#define GICC_IIDR_PID_SHIFT 20
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#define GICC_IIDR_ARCH_SHIFT 16
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#define GICC_IIDR_REV_SHIFT 12
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#define GICC_IIDR_IMP_SHIFT 0
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#define GICC_IIDR_PID_MASK 0xfff
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#define GICC_IIDR_ARCH_MASK 0xf
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#define GICC_IIDR_REV_MASK 0xf
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#define GICC_IIDR_IMP_MASK 0xfff
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/* HYP view virtual CPU Interface registers */
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#define GICH_CTL 0x0
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#define GICH_VTR 0x4
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#define GICH_ELRSR0 0x30
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#define GICH_ELRSR1 0x34
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#define GICH_APR0 0xF0
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#define GICH_LR_BASE 0x100
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/* Virtual CPU Interface registers */
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#define GICV_CTL 0x0
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#define GICV_PRIMASK 0x4
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#define GICV_BP 0x8
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#define GICV_INTACK 0xC
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#define GICV_EOI 0x10
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#define GICV_RUNNINGPRI 0x14
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#define GICV_HIGHESTPEND 0x18
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#define GICV_DEACTIVATE 0x1000
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/* GICD_CTLR bit definitions */
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#define CTLR_ENABLE_G1_SHIFT 1
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#define CTLR_ENABLE_G1_MASK 0x1
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#define CTLR_ENABLE_G1_BIT (1 << CTLR_ENABLE_G1_SHIFT)
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/* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
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#define INT_ID_MASK 0x3ff
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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/*******************************************************************************
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* This structure describes some of the implementation defined attributes of
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* the GICv2 IP. It is used by the platform port to specify these attributes
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* in order to initialize the GICv2 driver. The attributes are described
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* below.
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*
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* 1. The 'gicd_base' field contains the base address of the Distributor
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* interface programmer's view.
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*
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* 2. The 'gicc_base' field contains the base address of the CPU Interface
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* programmer's view.
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*
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* 3. The 'g0_interrupt_array' field is a pointer to an array in which each
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* entry corresponds to an ID of a Group 0 interrupt.
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*
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* 4. The 'g0_interrupt_num' field contains the number of entries in the
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* 'g0_interrupt_array'.
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******************************************************************************/
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typedef struct gicv2_driver_data {
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uintptr_t gicd_base;
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uintptr_t gicc_base;
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unsigned int g0_interrupt_num;
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const unsigned int *g0_interrupt_array;
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} gicv2_driver_data_t;
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/*******************************************************************************
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* Function prototypes
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******************************************************************************/
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void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data);
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void gicv2_distif_init(void);
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void gicv2_pcpu_distif_init(void);
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void gicv2_cpuif_enable(void);
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void gicv2_cpuif_disable(void);
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unsigned int gicv2_is_fiq_enabled(void);
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unsigned int gicv2_get_pending_interrupt_type(void);
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unsigned int gicv2_get_pending_interrupt_id(void);
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unsigned int gicv2_acknowledge_interrupt(void);
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void gicv2_end_of_interrupt(unsigned int id);
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unsigned int gicv2_get_interrupt_group(unsigned int id);
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#endif /* __ASSEMBLY__ */
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#endif /* __GICV2_H__ */
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