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https://github.com/ARM-software/arm-trusted-firmware.git
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e6ae019a84
This patch adds an API(plat_cluster_id_by_mpidr) that retrieves the cluster ID by looking at the MPIDR_EL1 for platforms that have ARM_PLAT_MT set Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com> Change-Id: I0266f2e49a3114d169a7708d7ddbd4f6229a7a41
75 lines
2.9 KiB
C
75 lines
2.9 KiB
C
/*
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* Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <plat/arm/common/plat_arm.h>
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#include <plat/arm/css/common/css_pm.h>
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#include <platform_def.h>
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/******************************************************************************
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* The power domain tree descriptor.
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******************************************************************************/
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const unsigned char tc_pd_tree_desc[] = {
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PLAT_ARM_CLUSTER_COUNT,
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PLAT_MAX_CPUS_PER_CLUSTER,
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};
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/*******************************************************************************
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* This function returns the topology tree information.
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******************************************************************************/
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const unsigned char *plat_get_power_domain_tree_desc(void)
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{
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return tc_pd_tree_desc;
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}
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/*******************************************************************************
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* The array mapping platform core position (implemented by plat_my_core_pos())
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* to the SCMI power domain ID implemented by SCP.
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******************************************************************************/
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const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
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#if PLATFORM_CORE_COUNT == 14
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
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(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
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#endif /* PLATFORM_CORE_COUNT == 14 */
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};
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/*******************************************************************************
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* This function returns the core count within the cluster corresponding to
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* `mpidr`.
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******************************************************************************/
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unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
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{
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return PLAT_MAX_CPUS_PER_CLUSTER;
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}
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#if ARM_PLAT_MT
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/******************************************************************************
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* Return the number of PE's supported by the CPU.
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*****************************************************************************/
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unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr)
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{
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return PLAT_MAX_PE_PER_CPU;
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}
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#endif
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/******************************************************************************
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* Return the cluster ID of current CPU
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*****************************************************************************/
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unsigned int plat_cluster_id_by_mpidr(u_register_t mpidr)
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{
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return MPIDR_AFFLVL2_VAL(mpidr);
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}
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