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b35ce0c413
DDR driver for NXP layerscape SoC(s): - lx2160aqds - lx2162aqds - lx2160ardb - Other Board with SoC(s) like ls1046a, ls1043a etc; -- These other boards are not verified yet. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Ic84a63cb30eba054f432d479862cd4d1097cbbaf
106 lines
2.4 KiB
C
106 lines
2.4 KiB
C
/*
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* Copyright 2021 NXP
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef _INPUT_H_
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#define _INPUT_H_
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enum dram_types {
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DDR4,
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DDR3,
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LPDDR4,
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LPDDR3,
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LPDDR2,
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DDR5,
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};
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enum dimm_types {
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UDIMM,
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SODIMM,
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RDIMM,
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LRDIMM,
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NODIMM,
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};
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struct input_basic {
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enum dram_types dram_type;
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enum dimm_types dimm_type;
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int lp4x_mode; /* 0x1 = lpddr4x mode, when dram_type is lpddr4
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*/
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/* not used for protocols other than lpddr4 */
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int num_dbyte; /* number of dbytes physically instantiated */
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int num_active_dbyte_dfi0; /* number of active dbytes to be
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* controlled by dfi0
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*/
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int num_active_dbyte_dfi1; /* number of active dbytes to be
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* controlled by dfi1. Not used for
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* protocols other than lpddr3 and
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* lpddr4
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*/
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int num_anib; /* number of anibs physically instantiated */
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int num_rank_dfi0; /* number of ranks in dfi0 channel */
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int num_rank_dfi1; /* number of ranks in dfi1 channel */
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int dram_data_width; /* 4,8,16 or 32 depending on protocol and dram
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* type
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*/
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int num_pstates;
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int frequency; /* memclk frequency in mhz -- round up */
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int pll_bypass; /* pll bypass enable */
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int dfi_freq_ratio; /* selected dfi frequency ratio */
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int dfi1exists; /* whether they phy config has dfi1 channel */
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int train2d;
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int hard_macro_ver;
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int read_dbienable;
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int dfi_mode; /* no longer used */
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};
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struct input_advanced {
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int d4rx_preamble_length;
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int d4tx_preamble_length;
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int ext_cal_res_val; /* external pull-down resistor */
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int is2ttiming;
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int odtimpedance;
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int tx_impedance;
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int atx_impedance;
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int mem_alert_en;
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int mem_alert_puimp;
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int mem_alert_vref_level;
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int mem_alert_sync_bypass;
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int dis_dyn_adr_tri;
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int phy_mstr_train_interval;
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int phy_mstr_max_req_to_ack;
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int wdqsext;
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int cal_interval;
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int cal_once;
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int dram_byte_swap;
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int rx_en_back_off;
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int train_sequence_ctrl;
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int phy_gen2_umctl_opt;
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int phy_gen2_umctl_f0rc5x;
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int tx_slew_rise_dq;
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int tx_slew_fall_dq;
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int tx_slew_rise_ac;
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int tx_slew_fall_ac;
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int enable_high_clk_skew_fix;
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int disable_unused_addr_lns;
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int phy_init_sequence_num;
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int cs_mode; /* rdimm */
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int cast_cs_to_cid; /* rdimm */
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};
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struct input {
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struct input_basic basic;
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struct input_advanced adv;
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unsigned int mr[7];
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unsigned int cs_d0;
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unsigned int cs_d1;
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unsigned int mirror;
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unsigned int odt[4];
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unsigned int rcw[16];
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unsigned int rcw3x;
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unsigned int vref;
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};
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#endif
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