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f3ccf036ec
This patch fixes the bug when AMUv1 group1 counters was always assumed being implemented without checking for its presence which was causing exception otherwise. The AMU extension code was also modified as listed below: - Added detection of AMUv1 for ARMv8.6 - 'PLAT_AMU_GROUP1_NR_COUNTERS' build option is removed and number of group1 counters 'AMU_GROUP1_NR_COUNTERS' is now calculated based on 'AMU_GROUP1_COUNTERS_MASK' value - Added bit fields definitions and access functions for AMCFGR_EL0/AMCFGR and AMCGCR_EL0/AMCGCR registers - Unification of amu.c Aarch64 and Aarch32 source files - Bug fixes and TF-A coding style compliant changes. Change-Id: I14e407be62c3026ebc674ec7045e240ccb71e1fb Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
19 lines
549 B
C
19 lines
549 B
C
/*
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef AMU_PRIVATE_H
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#define AMU_PRIVATE_H
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#include <stdint.h>
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uint64_t amu_group0_cnt_read_internal(unsigned int idx);
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void amu_group0_cnt_write_internal(unsigned int idx, uint64_t val);
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uint64_t amu_group1_cnt_read_internal(unsigned int idx);
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void amu_group1_cnt_write_internal(unsigned int idx, uint64_t val);
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void amu_group1_set_evtype_internal(unsigned int idx, unsigned int val);
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#endif /* AMU_PRIVATE_H */
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