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https://github.com/ARM-software/arm-trusted-firmware.git
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b2805dabaa
These directives are only used when stabs debugging information is used, but we use ELF which uses DWARF debugging information. Clang assembler doesn't support these directives, and removing them makes the code more compatible with clang. Change-Id: I2803f22ebd24c0fe248e04ef1b17de9cec5f89c4 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
213 lines
5.3 KiB
ArmAsm
213 lines
5.3 KiB
ArmAsm
/*
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* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __ASM_MACROS_S__
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#define __ASM_MACROS_S__
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#include <arch.h>
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#include <asm_macros_common.S>
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#include <spinlock.h>
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/*
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* TLBI instruction with type specifier that implements the workaround for
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* errata 813419 of Cortex-A57.
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*/
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#if ERRATA_A57_813419
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#define TLB_INVALIDATE(_type) \
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tlbi _type; \
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dsb ish; \
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tlbi _type
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#else
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#define TLB_INVALIDATE(_type) \
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tlbi _type
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#endif
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.macro func_prologue
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stp x29, x30, [sp, #-0x10]!
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mov x29,sp
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.endm
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.macro func_epilogue
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ldp x29, x30, [sp], #0x10
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.endm
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.macro dcache_line_size reg, tmp
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mrs \tmp, ctr_el0
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ubfx \tmp, \tmp, #16, #4
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mov \reg, #4
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lsl \reg, \reg, \tmp
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.endm
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.macro icache_line_size reg, tmp
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mrs \tmp, ctr_el0
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and \tmp, \tmp, #0xf
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mov \reg, #4
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lsl \reg, \reg, \tmp
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.endm
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.macro smc_check label
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mrs x0, esr_el3
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ubfx x0, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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cmp x0, #EC_AARCH64_SMC
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b.ne $label
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.endm
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/*
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* Declare the exception vector table, enforcing it is aligned on a
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* 2KB boundary, as required by the ARMv8 architecture.
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* Use zero bytes as the fill value to be stored in the padding bytes
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* so that it inserts illegal AArch64 instructions. This increases
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* security, robustness and potentially facilitates debugging.
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*/
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.macro vector_base label, section_name=.vectors
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.section \section_name, "ax"
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.align 11, 0
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\label:
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.endm
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/*
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* Create an entry in the exception vector table, enforcing it is
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* aligned on a 128-byte boundary, as required by the ARMv8 architecture.
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* Use zero bytes as the fill value to be stored in the padding bytes
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* so that it inserts illegal AArch64 instructions. This increases
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* security, robustness and potentially facilitates debugging.
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*/
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.macro vector_entry label, section_name=.vectors
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.cfi_sections .debug_frame
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.section \section_name, "ax"
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.align 7, 0
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.type \label, %function
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.cfi_startproc
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\label:
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.endm
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/*
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* This macro verifies that the given vector doesn't exceed the
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* architectural limit of 32 instructions. This is meant to be placed
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* immediately after the last instruction in the vector. It takes the
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* vector entry as the parameter
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*/
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.macro check_vector_size since
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.cfi_endproc
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.if (. - \since) > (32 * 4)
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.error "Vector exceeds 32 instructions"
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.endif
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.endm
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#if ENABLE_PLAT_COMPAT
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/*
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* This macro calculates the base address of an MP stack using the
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* platform_get_core_pos() index, the name of the stack storage and
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* the size of each stack
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* In: X0 = MPIDR of CPU whose stack is wanted
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* Out: X0 = physical address of stack base
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* Clobber: X30, X1, X2
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*/
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.macro get_mp_stack _name, _size
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bl platform_get_core_pos
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ldr x2, =(\_name + \_size)
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mov x1, #\_size
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madd x0, x0, x1, x2
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.endm
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#endif
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/*
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* This macro calculates the base address of the current CPU's MP stack
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* using the plat_my_core_pos() index, the name of the stack storage
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* and the size of each stack
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* Out: X0 = physical address of stack base
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* Clobber: X30, X1, X2
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*/
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.macro get_my_mp_stack _name, _size
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bl plat_my_core_pos
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ldr x2, =(\_name + \_size)
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mov x1, #\_size
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madd x0, x0, x1, x2
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.endm
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/*
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* This macro calculates the base address of a UP stack using the
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* name of the stack storage and the size of the stack
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* Out: X0 = physical address of stack base
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*/
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.macro get_up_stack _name, _size
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ldr x0, =(\_name + \_size)
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.endm
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/*
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* Helper macro to generate the best mov/movk combinations according
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* the value to be moved. The 16 bits from '_shift' are tested and
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* if not zero, they are moved into '_reg' without affecting
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* other bits.
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*/
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.macro _mov_imm16 _reg, _val, _shift
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.if (\_val >> \_shift) & 0xffff
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.if (\_val & (1 << \_shift - 1))
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movk \_reg, (\_val >> \_shift) & 0xffff, LSL \_shift
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.else
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mov \_reg, \_val & (0xffff << \_shift)
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.endif
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.endif
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.endm
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/*
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* Helper macro to load arbitrary values into 32 or 64-bit registers
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* which generates the best mov/movk combinations. Many base addresses
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* are 64KB aligned the macro will eliminate updating bits 15:0 in
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* that case
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*/
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.macro mov_imm _reg, _val
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.if (\_val) == 0
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mov \_reg, #0
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.else
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_mov_imm16 \_reg, (\_val), 0
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_mov_imm16 \_reg, (\_val), 16
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_mov_imm16 \_reg, (\_val), 32
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_mov_imm16 \_reg, (\_val), 48
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.endif
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.endm
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/*
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* Macro to mark instances where we're jumping to a function and don't
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* expect a return. To provide the function being jumped to with
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* additional information, we use 'bl' instruction to jump rather than
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* 'b'.
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*
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* Debuggers infer the location of a call from where LR points to, which
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* is usually the instruction after 'bl'. If this macro expansion
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* happens to be the last location in a function, that'll cause the LR
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* to point a location beyond the function, thereby misleading debugger
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* back trace. We therefore insert a 'nop' after the function call for
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* debug builds, unless 'skip_nop' parameter is non-zero.
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*/
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.macro no_ret _func:req, skip_nop=0
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bl \_func
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#if DEBUG
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.ifeq \skip_nop
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nop
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.endif
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#endif
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.endm
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/*
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* Reserve space for a spin lock in assembly file.
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*/
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.macro define_asm_spinlock _name:req
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.align SPINLOCK_ASM_ALIGN
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\_name:
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.space SPINLOCK_ASM_SIZE
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.endm
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#if RAS_EXTENSION
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.macro esb
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.inst 0xd503221f
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.endm
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#endif
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#endif /* __ASM_MACROS_S__ */
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