Govindraj Raja 306551362c feat(d128): add support for FEAT_D128 ... This patch disables trapping to EL3 when the FEAT_D128 specific registers are accessed by setting the SCR_EL3.D128En bit. If FEAT_D128 is implemented, then FEAT_SYSREG128 is implemented. With FEAT_SYSREG128 certain system registers are treated as 128-bit, so we should be context saving and restoring 128-bits instead of 64-bit when FEAT_D128 is enabled. FEAT_SYSREG128 adds support for MRRS and MSRR instruction which helps us to read write to 128-bit system register. Refer to Arm Architecture Manual for further details. Change the FVP platform to default to handling this as a dynamic option so the right decision can be made by the code at runtime. Change-Id: I1a53db5eac29e56c8fbdcd4961ede3abfcb2411a Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>		2024-10-24 14:51:55 -05:00
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arm_arch_svc	chore: simplify the macro names in ENABLE_FEAT mechanism	2024-05-02 08:53:01 -05:00
el3	refactor(smccc): move pmf to vendor el3 calls	2024-05-06 09:42:11 -05:00
oem/chromeos	feat(cros_widevine): add ChromeOS widevine SMC handler	2024-02-02 16:41:21 +08:00
spd	feat(d128): add support for FEAT_D128	2024-10-24 14:51:55 -05:00
std_svc	feat(rmmd): el3 token sign during attestation	2024-10-15 08:20:28 -07:00