Amit Nagal 93ed138006 fix(xilinx): dcache flush for dtb region ... flush dcache region for dtb so that dtb cache entries are first written to disk and are invalidated afterwards to avoid presence of any stale dtb related entry in the dcache. Change-Id: Ide0ed58f799b35b690ed790c7498ecdc334e02f5 Signed-off-by: Amit Nagal <amit.nagal@amd.com>		2023-09-13 18:37:39 +02:00
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common	fix(xilinx): dcache flush for dtb region	2023-09-13 18:37:39 +02:00
versal	fix(xilinx): dynamic mmap region for dtb	2023-09-13 18:36:00 +02:00
versal_net	fix(versal-net): don't clear pending interrupts	2023-08-17 12:37:05 -07:00
zynqmp	fix(zynqmp): validate clock_id to avoid OOB variable access	2023-08-17 05:42:28 -07:00