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b139f1cf97
The Arm(R) Ethos(TM)-N NPU driver now supports configuring the SMMU streams that the NPU shall use and will therefore no longer delegate access to these registers to the non-secure world. In order for the driver to support this, the device tree parsing has been updated to support parsing the allocators used by the NPU and what SMMU stream that is associated with each allocator. To keep track of what NPU device each allocator is associated with, the resulting config from the device tree parsing will now group the NPU cores and allocators into their respective NPU device. The SMC API has been changed to allow the caller to specify what allocator the NPU shall be configured to use and the API version has been bumped to indicate this change. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I6ac43819133138614e3f55a014e93466fe3d5277
38 lines
957 B
C
38 lines
957 B
C
/*
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* Copyright (c) 2016-2019,2021-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ARM_SIP_SVC_H
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#define ARM_SIP_SVC_H
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#include <lib/utils_def.h>
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/* SMC function IDs for SiP Service queries */
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#define ARM_SIP_SVC_CALL_COUNT U(0x8200ff00)
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#define ARM_SIP_SVC_UID U(0x8200ff01)
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/* U(0x8200ff02) is reserved */
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#define ARM_SIP_SVC_VERSION U(0x8200ff03)
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/* PMF_SMC_GET_TIMESTAMP_32 0x82000010 */
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/* PMF_SMC_GET_TIMESTAMP_64 0xC2000010 */
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/* Function ID for requesting state switch of lower EL */
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#define ARM_SIP_SVC_EXE_STATE_SWITCH U(0x82000020)
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/* DEBUGFS_SMC_32 0x82000030U */
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/* DEBUGFS_SMC_64 0xC2000030U */
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/*
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* Arm(R) Ethos(TM)-N NPU SiP SMC function IDs
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* 0xC2000050-0xC200005F
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* 0x82000050-0x8200005F
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*/
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/* ARM SiP Service Calls version numbers */
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#define ARM_SIP_SVC_VERSION_MAJOR U(0x0)
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#define ARM_SIP_SVC_VERSION_MINOR U(0x2)
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#endif /* ARM_SIP_SVC_H */
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