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b10d44995e
In AArch64, privileged exception levels control the execution state
(a.k.a. register width) of the immediate lower Exception Level; i.e.
whether the lower exception level executes in AArch64 or AArch32 state.
For an exception level to have its execution state changed at run time,
it must request the change by raising a synchronous exception to the
higher exception level.
This patch implements and adds such a provision to the ARM SiP service,
by which an immediate lower exception level can request to switch its
execution state. The execution state is switched if the request is:
- raised from non-secure world;
- raised on the primary CPU, before any secondaries are brought online
with CPU_ON PSCI call;
- raised from an exception level immediately below EL3: EL2, if
implemented; otherwise NS EL1.
If successful, the SMC doesn't return to the caller, but to the entry
point supplied with the call. Otherwise, the caller will observe the SMC
returning with STATE_SW_E_DENIED code. If ARM Trusted Firmware is built
for AArch32, the feature is not supported, and the call will always
fail.
For the ARM SiP service:
- Add SMC function IDs for both AArch32 and AArch64;
- Increment the SiP service minor version to 2;
- Adjust the number of supported SiP service calls.
Add documentation for ARM SiP service.
Fixes ARM-software/tf-issues#436
Change-Id: I4347f2d6232e69fbfbe333b340fcd0caed0a4cea
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
117 lines
4.6 KiB
C
117 lines
4.6 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PSCI_LIB_H__
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#define __PSCI_LIB_H__
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#include <ep_info.h>
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#ifndef __ASSEMBLY__
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#include <types.h>
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/*******************************************************************************
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* Optional structure populated by the Secure Payload Dispatcher to be given a
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* chance to perform any bookkeeping before PSCI executes a power management
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* operation. It also allows PSCI to determine certain properties of the SP e.g.
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* migrate capability etc.
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******************************************************************************/
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typedef struct spd_pm_ops {
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void (*svc_on)(u_register_t target_cpu);
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int32_t (*svc_off)(u_register_t __unused);
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void (*svc_suspend)(u_register_t max_off_pwrlvl);
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void (*svc_on_finish)(u_register_t __unused);
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void (*svc_suspend_finish)(u_register_t max_off_pwrlvl);
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int32_t (*svc_migrate)(u_register_t from_cpu, u_register_t to_cpu);
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int32_t (*svc_migrate_info)(u_register_t *resident_cpu);
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void (*svc_system_off)(void);
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void (*svc_system_reset)(void);
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} spd_pm_ops_t;
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/*
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* Function prototype for the warmboot entrypoint function which will be
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* programmed in the mailbox by the platform.
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*/
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typedef void (*mailbox_entrypoint_t)(void);
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/******************************************************************************
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* Structure to pass PSCI Library arguments.
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*****************************************************************************/
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typedef struct psci_lib_args {
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/* The version information of PSCI Library Interface */
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param_header_t h;
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/* The warm boot entrypoint function */
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mailbox_entrypoint_t mailbox_ep;
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} psci_lib_args_t;
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/* Helper macro to set the psci_lib_args_t structure at runtime */
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#define SET_PSCI_LIB_ARGS_V1(_p, _entry) do { \
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SET_PARAM_HEAD(_p, PARAM_PSCI_LIB_ARGS, VERSION_1, 0); \
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(_p)->mailbox_ep = (_entry); \
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} while (0)
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/* Helper macro to define the psci_lib_args_t statically */
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#define DEFINE_STATIC_PSCI_LIB_ARGS_V1(_name, _entry) \
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static const psci_lib_args_t (_name) = { \
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.h.type = (uint8_t)PARAM_PSCI_LIB_ARGS, \
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.h.version = (uint8_t)VERSION_1, \
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.h.size = (uint16_t)sizeof(_name), \
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.h.attr = 0, \
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.mailbox_ep = (_entry) \
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}
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/* Helper macro to verify the pointer to psci_lib_args_t structure */
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#define VERIFY_PSCI_LIB_ARGS_V1(_p) ((_p) \
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&& ((_p)->h.type == PARAM_PSCI_LIB_ARGS) \
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&& ((_p)->h.version == VERSION_1) \
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&& ((_p)->h.size == sizeof(*(_p))) \
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&& ((_p)->h.attr == 0) \
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&& ((_p)->mailbox_ep))
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/******************************************************************************
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* PSCI Library Interfaces
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*****************************************************************************/
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u_register_t psci_smc_handler(uint32_t smc_fid,
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u_register_t x1,
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u_register_t x2,
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u_register_t x3,
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u_register_t x4,
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void *cookie,
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void *handle,
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u_register_t flags);
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int psci_setup(const psci_lib_args_t *lib_args);
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int psci_secondaries_brought_up(void);
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void psci_warmboot_entrypoint(void);
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void psci_register_spd_pm_hook(const spd_pm_ops_t *pm);
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void psci_prepare_next_non_secure_ctx(
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entry_point_info_t *next_image_info);
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#endif /* __ASSEMBLY__ */
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#endif /* __PSCI_LIB_H */
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