mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 18:14:24 +00:00
c19a82bef0
This change enables MPMM and adds, to the TC firmware configuration device tree, the AMU counters representing the "gears" for the Maximum Power Mitigation Mechanism feature of the Cortex-X2, Cortex-A710 and Cortex-A510: - Gear 0: throttle medium and high bandwidth vector and viruses. - Gear 1: throttle high bandwidth vector and viruses. - Gear 2: throttle power viruses only. This ensures these counters are enabled and context-switched as expected. Change-Id: I6df6e0fe3a5362861aa967a78ab7c34fc4bb8fc3 Signed-off-by: Chris Kay <chris.kay@arm.com>
479 lines
9.6 KiB
Text
479 lines
9.6 KiB
Text
/*
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* Copyright (c) 2020-2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/dts-v1/;
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/ {
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compatible = "arm,tc";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &soc_uart0;
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};
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chosen {
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bootargs = "console=ttyAMA0 debug user_debug=31 earlycon=pl011,0x7ff80000 loglevel=9 androidboot.hardware=total_compute androidboot.boot_devices=1c050000.mmci ip=dhcp androidboot.selinux=permissive allow_mismatched_32bit_el0";
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stdout-path = "serial0:115200n8";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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core6 {
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cpu = <&CPU6>;
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};
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core7 {
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cpu = <&CPU7>;
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};
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};
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};
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/*
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* The timings below are just to demonstrate working cpuidle.
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* These values may be inaccurate.
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*/
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idle-states {
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entry-method = "arm,psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x0010000>;
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local-timer-stop;
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entry-latency-us = <300>;
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exit-latency-us = <1200>;
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min-residency-us = <2000>;
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};
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x1010000>;
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local-timer-stop;
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entry-latency-us = <400>;
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exit-latency-us = <1200>;
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min-residency-us = <2500>;
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};
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};
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amus {
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amu: amu-0 {
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#address-cells = <1>;
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#size-cells = <0>;
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mpmm_gear0: counter@0 {
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reg = <0>;
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enable-at-el3;
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};
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mpmm_gear1: counter@1 {
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reg = <1>;
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enable-at-el3;
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};
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mpmm_gear2: counter@2 {
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reg = <2>;
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enable-at-el3;
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};
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};
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};
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CPU0:cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <406>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU1:cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x100>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <406>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU2:cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x200>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <406>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU3:cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x300>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 0>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <406>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU4:cpu@400 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x400>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <912>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU5:cpu@500 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x500>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <912>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU6:cpu@600 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x600>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 1>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <912>;
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amu = <&amu>;
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supports-mpmm;
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};
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CPU7:cpu@700 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x700>;
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enable-method = "psci";
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clocks = <&scmi_dvfs 2>;
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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capacity-dmips-mhz = <1024>;
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amu = <&amu>;
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supports-mpmm;
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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optee@0xfce00000 {
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reg = <0x00000000 0xfce00000 0 0x00200000>;
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no-map;
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};
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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};
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sram: sram@6000000 {
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compatible = "mmio-sram";
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reg = <0x0 0x06000000 0x0 0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x06000000 0x8000>;
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cpu_scp_scmi_mem: scp-shmem@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x80>;
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};
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};
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mbox_db_rx: mhu@45010000 {
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compatible = "arm,mhuv2-rx","arm,primecell";
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reg = <0x0 0x45010000 0x0 0x1000>;
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clocks = <&soc_refclk100mhz>;
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clock-names = "apb_pclk";
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#mbox-cells = <2>;
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interrupts = <0 317 4>;
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interrupt-names = "mhu_rx";
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mhu-protocol = "doorbell";
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arm,mhuv2-protocols = <0 1>;
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};
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mbox_db_tx: mhu@45000000 {
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compatible = "arm,mhuv2-tx","arm,primecell";
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reg = <0x0 0x45000000 0x0 0x1000>;
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clocks = <&soc_refclk100mhz>;
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clock-names = "apb_pclk";
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#mbox-cells = <2>;
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interrupt-names = "mhu_tx";
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mhu-protocol = "doorbell";
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arm,mhuv2-protocols = <0 1>;
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};
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scmi {
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compatible = "arm,scmi";
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mbox-names = "tx", "rx";
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mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >;
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shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_dvfs: protocol@13 {
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reg = <0x13>;
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#clock-cells = <1>;
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};
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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};
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gic: interrupt-controller@2c010000 {
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compatible = "arm,gic-600", "arm,gic-v3";
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#address-cells = <2>;
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#interrupt-cells = <3>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0x30000000 0 0x10000>, /* GICD */
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<0x0 0x30080000 0 0x200000>; /* GICR */
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interrupts = <0x1 0x9 0x4>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <0x1 13 0x8>,
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<0x1 14 0x8>,
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<0x1 11 0x8>,
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<0x1 10 0x8>;
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};
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soc_refclk100mhz: refclk100mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "apb_pclk";
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};
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soc_refclk60mhz: refclk60mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <60000000>;
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clock-output-names = "iofpga_clk";
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};
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soc_uartclk: uartclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "uartclk";
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};
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soc_uart0: uart@7ff80000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x7ff80000 0x0 0x1000>;
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interrupts = <0x0 116 0x4>;
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clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
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clock-names = "uartclk", "apb_pclk";
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status = "okay";
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};
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vencoder {
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compatible = "drm,virtual-encoder";
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port {
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vencoder_in: endpoint {
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remote-endpoint = <&dp_pl0_out0>;
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};
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};
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display-timings {
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panel-timing {
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clock-frequency = <25175000>;
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hactive = <640>;
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vactive = <480>;
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hfront-porch = <16>;
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hback-porch = <48>;
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hsync-len = <96>;
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vfront-porch = <10>;
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vback-porch = <33>;
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vsync-len = <2>;
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};
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};
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};
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hdlcd: hdlcd@7ff60000 {
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compatible = "arm,hdlcd";
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reg = <0x0 0x7ff60000 0x0 0x1000>;
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interrupts = <0x0 117 0x4>;
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clocks = <&fake_hdlcd_clk>;
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clock-names = "pxlclk";
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status = "disabled";
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port {
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hdlcd_out: endpoint {
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remote-endpoint = <&vencoder_in>;
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};
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};
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};
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fake_hdlcd_clk: fake-hdlcd-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25175000>;
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clock-output-names = "pxlclk";
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};
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ethernet@18000000 {
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compatible = "smsc,lan91c111";
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reg = <0x0 0x18000000 0x0 0x10000>;
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interrupts = <0 109 4>;
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};
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kmi@1c060000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x001c060000 0x0 0x1000>;
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interrupts = <0 197 4>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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kmi@1c070000 {
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compatible = "arm,pl050", "arm,primecell";
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reg = <0x0 0x001c070000 0x0 0x1000>;
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interrupts = <0 103 4>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "KMIREFCLK", "apb_pclk";
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};
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bp_clock24mhz: clock24mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "bp:clock24mhz";
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};
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virtio_block@1c130000 {
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compatible = "virtio,mmio";
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reg = <0x0 0x1c130000 0x0 0x200>;
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interrupts = <0 204 4>;
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};
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sysreg: sysreg@1c010000 {
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compatible = "arm,vexpress-sysreg";
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reg = <0x0 0x001c010000 0x0 0x1000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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fixed_3v3: v2m-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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mmci@1c050000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x0 0x001c050000 0x0 0x1000>;
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interrupts = <0 107 0x4>,
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<0 108 0x4>;
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cd-gpios = <&sysreg 0 0>;
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wp-gpios = <&sysreg 1 0>;
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bus-width = <8>;
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max-frequency = <12000000>;
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vmmc-supply = <&fixed_3v3>;
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clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
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clock-names = "mclk", "apb_pclk";
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};
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dp0: display@2cc00000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "arm,mali-d71";
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reg = <0 0x2cc00000 0 0x20000>;
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interrupts = <0 69 4>;
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interrupt-names = "DPU";
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clocks = <&scmi_clk 0>;
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clock-names = "aclk";
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pl0: pipeline@0 {
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reg = <0>;
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clocks = <&scmi_clk 1>;
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clock-names = "pxclk";
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pl_id = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dp_pl0_out0: endpoint {
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remote-endpoint = <&vencoder_in>;
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};
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};
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};
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};
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pl1: pipeline@1 {
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reg = <1>;
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clocks = <&scmi_clk 2>;
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clock-names = "pxclk";
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pl_id = <1>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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};
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};
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};
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};
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};
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