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b053a22e8a
STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4. The support for Cortex-M4 clocks is added when configuring the clock tree. Some minimal security features to allow communications between A7 and M4 are also added. Change-Id: I60417e244a476f60a2758f4969700b2684056665 Signed-off-by: Yann Gautier <yann.gautier@st.com>
49 lines
1.1 KiB
C
49 lines
1.1 KiB
C
/*
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* Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32MP1_CLK_H
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#define STM32MP1_CLK_H
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#include <arch_helpers.h>
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int stm32mp1_clk_probe(void);
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int stm32mp1_clk_init(void);
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bool stm32mp1_rcc_is_secure(void);
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bool stm32mp1_rcc_is_mckprot(void);
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void __stm32mp1_clk_enable(unsigned long id, bool caller_is_secure);
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void __stm32mp1_clk_disable(unsigned long id, bool caller_is_secure);
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static inline void stm32mp1_clk_enable_non_secure(unsigned long id)
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{
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__stm32mp1_clk_enable(id, false);
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}
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static inline void stm32mp1_clk_enable_secure(unsigned long id)
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{
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__stm32mp1_clk_enable(id, true);
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}
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static inline void stm32mp1_clk_disable_non_secure(unsigned long id)
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{
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__stm32mp1_clk_disable(id, false);
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}
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static inline void stm32mp1_clk_disable_secure(unsigned long id)
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{
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__stm32mp1_clk_disable(id, true);
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}
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unsigned int stm32mp1_clk_get_refcount(unsigned long id);
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/* SMP protection on RCC registers access */
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void stm32mp1_clk_rcc_regs_lock(void);
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void stm32mp1_clk_rcc_regs_unlock(void);
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void stm32mp1_stgen_increment(unsigned long long offset_in_ms);
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#endif /* STM32MP1_CLK_H */
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