Bipin Ravi afc2ed63f9 errata: workaround for Cortex-A710 erratum 2017096 ... Cortex-A710 erratum 2017096 is a Cat B erratum that applies to revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to set CPUECLTR_EL1[8] to 1 which disables store issue prefetching. SDEN can be found here: https://developer.arm.com/documentation/SDEN1775101/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3		2021-09-03 15:44:56 -05:00
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alt-boot-flows.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
auth-framework.rst	Cleanup the code for TBBR CoT descriptors	2020-05-19 05:05:19 +01:00
cpu-specific-build-macros.rst	errata: workaround for Cortex-A710 erratum 2017096	2021-09-03 15:44:56 -05:00
firmware-design.rst	doc: Correct CPACR.FPEN usage	2020-09-14 02:35:50 +00:00
index.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
interrupt-framework-design.rst	Fix broken links to various sections across docs	2020-08-03 09:55:04 -05:00
psci-pd-tree.rst	doc: Set correct syntax highlighting style	2019-05-22 11:28:17 +01:00
reset-design.rst	doc: Split the User Guide into multiple files	2019-11-27 10:45:54 +00:00
trusted-board-boot-build.rst	Mention COT build option in trusted-board-boot-build.rst	2020-03-12 17:11:26 +01:00
trusted-board-boot.rst	Update cryptographic algorithms in TBBR doc	2020-03-12 17:11:25 +01:00