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https://github.com/ARM-software/arm-trusted-firmware.git
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8668fe0c80
DRBG must be initialized to guarantee SRK has a random value during suspend. This patch add a sequence to generate an SRK on boot and during resume for SE1 and SE2. This SRK value is not saved to PMC scratch, and should be overwitten during atomic suspend. Change-Id: Id5e2dc74a1b462dd6addaec1709fec46083a6e1c Signed-off-by: Sam Payne <spayne@nvidia.com>
503 lines
14 KiB
C
503 lines
14 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <assert.h>
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#include <common/debug.h>
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#include <delay_timer.h>
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#include <errno.h>
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#include <mmio.h>
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#include <psci.h>
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#include <se_private.h>
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#include <security_engine.h>
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#include <tegra_platform.h>
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/*******************************************************************************
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* Constants and Macros
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******************************************************************************/
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#define TIMEOUT_100MS 100UL // Timeout in 100ms
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/*******************************************************************************
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* Data structure and global variables
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******************************************************************************/
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/* The security engine contexts are formatted as follows:
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*
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* SE1 CONTEXT:
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* #--------------------------------#
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* | Random Data 1 Block |
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* #--------------------------------#
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* | Sticky Bits 2 Blocks |
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* #--------------------------------#
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* | Key Table 64 Blocks |
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* | For each Key (x16): |
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* | Key: 2 Blocks |
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* | Original-IV: 1 Block |
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* | Updated-IV: 1 Block |
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* #--------------------------------#
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* | RSA Keys 64 Blocks |
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* #--------------------------------#
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* | Known Pattern 1 Block |
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* #--------------------------------#
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*
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* SE2/PKA1 CONTEXT:
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* #--------------------------------#
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* | Random Data 1 Block |
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* #--------------------------------#
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* | Sticky Bits 2 Blocks |
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* #--------------------------------#
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* | Key Table 64 Blocks |
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* | For each Key (x16): |
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* | Key: 2 Blocks |
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* | Original-IV: 1 Block |
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* | Updated-IV: 1 Block |
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* #--------------------------------#
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* | RSA Keys 64 Blocks |
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* #--------------------------------#
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* | PKA sticky bits 1 Block |
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* #--------------------------------#
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* | PKA keys 512 Blocks |
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* #--------------------------------#
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* | Known Pattern 1 Block |
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* #--------------------------------#
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*/
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/* SE input and output linked list buffers */
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static tegra_se_io_lst_t se1_src_ll_buf;
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static tegra_se_io_lst_t se1_dst_ll_buf;
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/* SE2 input and output linked list buffers */
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static tegra_se_io_lst_t se2_src_ll_buf;
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static tegra_se_io_lst_t se2_dst_ll_buf;
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/* SE1 security engine device handle */
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static tegra_se_dev_t se_dev_1 = {
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.se_num = 1,
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/* setup base address for se */
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.se_base = TEGRA_SE1_BASE,
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/* Setup context size in AES blocks */
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.ctx_size_blks = SE_CTX_SAVE_SIZE_BLOCKS_SE1,
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/* Setup SRC buffers for SE operations */
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.src_ll_buf = &se1_src_ll_buf,
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/* Setup DST buffers for SE operations */
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.dst_ll_buf = &se1_dst_ll_buf,
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};
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/* SE2 security engine device handle */
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static tegra_se_dev_t se_dev_2 = {
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.se_num = 2,
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/* setup base address for se */
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.se_base = TEGRA_SE2_BASE,
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/* Setup context size in AES blocks */
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.ctx_size_blks = SE_CTX_SAVE_SIZE_BLOCKS_SE2,
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/* Setup SRC buffers for SE operations */
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.src_ll_buf = &se2_src_ll_buf,
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/* Setup DST buffers for SE operations */
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.dst_ll_buf = &se2_dst_ll_buf,
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};
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/*******************************************************************************
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* Functions Definition
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******************************************************************************/
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static void tegra_se_make_data_coherent(const tegra_se_dev_t *se_dev)
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{
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flush_dcache_range(((uint64_t)(se_dev->src_ll_buf)),
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sizeof(tegra_se_io_lst_t));
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flush_dcache_range(((uint64_t)(se_dev->dst_ll_buf)),
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sizeof(tegra_se_io_lst_t));
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}
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/*
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* Check that SE operation has completed after kickoff
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* This function is invoked after an SE operation has been started,
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* and it checks the following conditions:
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* 1. SE_INT_STATUS = SE_OP_DONE
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* 2. SE_STATUS = IDLE
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* 3. AHB bus data transfer complete.
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* 4. SE_ERR_STATUS is clean.
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*/
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static int32_t tegra_se_operation_complete(const tegra_se_dev_t *se_dev)
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{
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uint32_t val = 0;
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int32_t ret = 0;
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uint32_t timeout;
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/* Poll the SE interrupt register to ensure H/W operation complete */
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val = tegra_se_read_32(se_dev, SE_INT_STATUS_REG_OFFSET);
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for (timeout = 0; (SE_INT_OP_DONE(val) == SE_INT_OP_DONE_CLEAR) &&
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(timeout < TIMEOUT_100MS); timeout++) {
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mdelay(1);
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val = tegra_se_read_32(se_dev, SE_INT_STATUS_REG_OFFSET);
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}
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if (timeout == TIMEOUT_100MS) {
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ERROR("%s: ERR: Atomic context save operation timeout!\n",
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__func__);
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ret = -ETIMEDOUT;
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}
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/* Poll the SE status idle to ensure H/W operation complete */
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if (ret == 0) {
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val = tegra_se_read_32(se_dev, SE_STATUS_OFFSET);
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for (timeout = 0; (val != 0U) && (timeout < TIMEOUT_100MS);
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timeout++) {
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mdelay(1);
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val = tegra_se_read_32(se_dev, SE_STATUS_OFFSET);
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}
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if (timeout == TIMEOUT_100MS) {
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ERROR("%s: ERR: MEM_INTERFACE and SE state "
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"idle state timeout.\n", __func__);
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ret = -ETIMEDOUT;
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}
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}
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/* Check AHB bus transfer complete */
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if (ret == 0) {
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val = mmio_read_32(TEGRA_AHB_ARB_BASE + ARAHB_MEM_WRQUE_MST_ID_OFFSET);
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for (timeout = 0; ((val & (ARAHB_MST_ID_SE_MASK | ARAHB_MST_ID_SE2_MASK)) != 0U) &&
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(timeout < TIMEOUT_100MS); timeout++) {
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mdelay(1);
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val = mmio_read_32(TEGRA_AHB_ARB_BASE + ARAHB_MEM_WRQUE_MST_ID_OFFSET);
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}
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if (timeout == TIMEOUT_100MS) {
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ERROR("%s: SE write over AHB timeout.\n", __func__);
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ret = -ETIMEDOUT;
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}
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}
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/* Ensure that no errors are thrown during operation */
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if (ret == 0) {
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val = tegra_se_read_32(se_dev, SE_ERR_STATUS_REG_OFFSET);
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if (val != 0U) {
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ERROR("%s: error during SE operation! 0x%x", __func__, val);
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ret = -ENOTSUP;
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}
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}
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return ret;
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}
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/*
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* Verify the SE context save auto has been enabled.
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* SE_CTX_SAVE_AUTO.ENABLE == ENABLE
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* If the SE context save auto is not enabled, then set
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* the context save auto enable and lock the setting.
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* If the SE context save auto is not enabled and the
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* enable setting is locked, then return an error.
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*/
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static inline int32_t tegra_se_ctx_save_auto_enable(const tegra_se_dev_t *se_dev)
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{
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uint32_t val;
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int32_t ret = 0;
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val = tegra_se_read_32(se_dev, SE_CTX_SAVE_AUTO_REG_OFFSET);
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if (SE_CTX_SAVE_AUTO_ENABLE(val) == SE_CTX_SAVE_AUTO_DIS) {
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if (SE_CTX_SAVE_AUTO_LOCK(val) == SE_CTX_SAVE_AUTO_LOCK_EN) {
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ERROR("%s: ERR: Cannot enable atomic. Write locked!\n",
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__func__);
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ret = -EACCES;
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}
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/* Program SE_CTX_SAVE_AUTO */
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if (ret == 0) {
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tegra_se_write_32(se_dev, SE_CTX_SAVE_AUTO_REG_OFFSET,
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SE_CTX_SAVE_AUTO_LOCK_EN |
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SE_CTX_SAVE_AUTO_EN);
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}
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}
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return ret;
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}
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/*
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* Wait for SE engine to be idle and clear pending interrupts before
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* starting the next SE operation.
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*/
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static int32_t tegra_se_operation_prepare(const tegra_se_dev_t *se_dev)
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{
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int32_t ret = 0;
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uint32_t val = 0;
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uint32_t timeout;
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/* Wait for previous operation to finish */
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val = tegra_se_read_32(se_dev, SE_STATUS_OFFSET);
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for (timeout = 0; (val != 0U) && (timeout < TIMEOUT_100MS); timeout++) {
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mdelay(1);
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val = tegra_se_read_32(se_dev, SE_STATUS_OFFSET);
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}
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if (timeout == TIMEOUT_100MS) {
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ERROR("%s: ERR: SE status is not idle!\n", __func__);
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ret = -ETIMEDOUT;
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}
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/* Clear any pending interrupts from previous operation */
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val = tegra_se_read_32(se_dev, SE_INT_STATUS_REG_OFFSET);
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tegra_se_write_32(se_dev, SE_INT_STATUS_REG_OFFSET, val);
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return ret;
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}
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/*
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* SE atomic context save. At SC7 entry, SE driver triggers the
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* hardware automatically performs the context save operation.
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*/
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static int32_t tegra_se_context_save_atomic(const tegra_se_dev_t *se_dev)
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{
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int32_t ret = 0;
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uint32_t val = 0;
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uint32_t blk_count_limit = 0;
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uint32_t block_count;
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/* Check that previous operation is finalized */
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ret = tegra_se_operation_prepare(se_dev);
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/* Ensure HW atomic context save has been enabled
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* This should have been done at boot time.
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* SE_CTX_SAVE_AUTO.ENABLE == ENABLE
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*/
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if (ret == 0) {
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ret = tegra_se_ctx_save_auto_enable(se_dev);
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}
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/* Read the context save progress counter: block_count
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* Ensure no previous context save has been triggered
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* SE_CTX_SAVE_AUTO.CURR_CNT == 0
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*/
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if (ret == 0) {
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val = tegra_se_read_32(se_dev, SE_CTX_SAVE_AUTO_REG_OFFSET);
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block_count = SE_CTX_SAVE_GET_BLK_COUNT(val);
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if (block_count != 0U) {
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ERROR("%s: ctx_save triggered multiple times\n",
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__func__);
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ret = -EALREADY;
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}
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}
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/* Set the destination block count when the context save complete */
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if (ret == 0) {
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blk_count_limit = block_count + se_dev->ctx_size_blks;
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}
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/* Program SE_CONFIG register as for RNG operation
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* SE_CONFIG.ENC_ALG = RNG
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* SE_CONFIG.DEC_ALG = NOP
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* SE_CONFIG.ENC_MODE is ignored
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* SE_CONFIG.DEC_MODE is ignored
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* SE_CONFIG.DST = MEMORY
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*/
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if (ret == 0) {
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val = (SE_CONFIG_ENC_ALG_RNG |
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SE_CONFIG_DEC_ALG_NOP |
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SE_CONFIG_DST_MEMORY);
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tegra_se_write_32(se_dev, SE_CONFIG_REG_OFFSET, val);
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tegra_se_make_data_coherent(se_dev);
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/* SE_CTX_SAVE operation */
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tegra_se_write_32(se_dev, SE_OPERATION_REG_OFFSET,
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SE_OP_CTX_SAVE);
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ret = tegra_se_operation_complete(se_dev);
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}
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/* Check that context has written the correct number of blocks */
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if (ret == 0) {
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val = tegra_se_read_32(se_dev, SE_CTX_SAVE_AUTO_REG_OFFSET);
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if (SE_CTX_SAVE_GET_BLK_COUNT(val) != blk_count_limit) {
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ERROR("%s: expected %d blocks but %d were written\n",
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__func__, blk_count_limit, val);
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ret = -ECANCELED;
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}
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}
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return ret;
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}
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/*
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* Security engine primitive operations, including normal operation
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* and the context save operation.
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*/
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static int tegra_se_perform_operation(const tegra_se_dev_t *se_dev, uint32_t nbytes)
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{
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uint32_t nblocks = nbytes / TEGRA_SE_AES_BLOCK_SIZE;
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int ret = 0;
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assert(se_dev);
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/* Use device buffers for in and out */
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tegra_se_write_32(se_dev, SE_OUT_LL_ADDR_REG_OFFSET, ((uint64_t)(se_dev->dst_ll_buf)));
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tegra_se_write_32(se_dev, SE_IN_LL_ADDR_REG_OFFSET, ((uint64_t)(se_dev->src_ll_buf)));
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/* Check that previous operation is finalized */
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ret = tegra_se_operation_prepare(se_dev);
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if (ret != 0) {
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goto op_error;
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}
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/* Program SE operation size */
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if (nblocks) {
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tegra_se_write_32(se_dev, SE_BLOCK_COUNT_REG_OFFSET, nblocks - 1);
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}
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/* Make SE LL data coherent before the SE operation */
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tegra_se_make_data_coherent(se_dev);
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/* Start hardware operation */
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tegra_se_write_32(se_dev, SE_OPERATION_REG_OFFSET, SE_OP_START);
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/* Wait for operation to finish */
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ret = tegra_se_operation_complete(se_dev);
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op_error:
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return ret;
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}
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/*
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* Security Engine sequence to generat SRK
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* SE and SE2 will generate different SRK by different
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* entropy seeds.
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*/
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static int tegra_se_generate_srk(const tegra_se_dev_t *se_dev)
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{
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int ret = PSCI_E_INTERN_FAIL;
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uint32_t val;
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/* Confgure the following hardware register settings:
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* SE_CONFIG.DEC_ALG = NOP
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* SE_CONFIG.ENC_ALG = RNG
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* SE_CONFIG.DST = SRK
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* SE_OPERATION.OP = START
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* SE_CRYPTO_LAST_BLOCK = 0
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*/
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se_dev->src_ll_buf->last_buff_num = 0;
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se_dev->dst_ll_buf->last_buff_num = 0;
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/* Configure random number generator */
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val = (DRBG_MODE_FORCE_RESEED | DRBG_SRC_ENTROPY);
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tegra_se_write_32(se_dev, SE_RNG_CONFIG_REG_OFFSET, val);
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/* Configure output destination = SRK */
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val = (SE_CONFIG_ENC_ALG_RNG |
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SE_CONFIG_DEC_ALG_NOP |
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SE_CONFIG_DST_SRK);
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tegra_se_write_32(se_dev, SE_CONFIG_REG_OFFSET, val);
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/* Perform hardware operation */
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ret = tegra_se_perform_operation(se_dev, 0);
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return ret;
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}
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/*
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* Initialize the SE engine handle
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*/
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void tegra_se_init(void)
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{
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INFO("%s: start SE init\n", __func__);
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/* Generate random SRK to initialize DRBG */
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tegra_se_generate_srk(&se_dev_1);
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tegra_se_generate_srk(&se_dev_2);
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INFO("%s: SE init done\n", __func__);
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}
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/*
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* Security engine power suspend entry point.
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* This function is invoked from PSCI power domain suspend handler.
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*/
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int32_t tegra_se_suspend(void)
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{
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int32_t ret = 0;
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/* Atomic context save se2 and pka1 */
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INFO("%s: SE2/PKA1 atomic context save\n", __func__);
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ret = tegra_se_context_save_atomic(&se_dev_2);
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/* Atomic context save se */
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if (ret == 0) {
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INFO("%s: SE1 atomic context save\n", __func__);
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ret = tegra_se_context_save_atomic(&se_dev_1);
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}
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if (ret == 0) {
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INFO("%s: SE atomic context save done\n", __func__);
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}
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return ret;
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}
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/*
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* Save TZRAM to shadow TZRAM in AON
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*/
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int32_t tegra_se_save_tzram(void)
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{
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uint32_t val = 0;
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int32_t ret = 0;
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uint32_t timeout;
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INFO("%s: SE TZRAM save start\n", __func__);
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val = (SE_TZRAM_OP_REQ_INIT | SE_TZRAM_OP_MODE_SAVE);
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tegra_se_write_32(&se_dev_1, SE_TZRAM_OPERATION, val);
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val = tegra_se_read_32(&se_dev_1, SE_TZRAM_OPERATION);
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for (timeout = 0; (SE_TZRAM_OP_BUSY(val) == SE_TZRAM_OP_BUSY_ON) &&
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(timeout < TIMEOUT_100MS); timeout++) {
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mdelay(1);
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val = tegra_se_read_32(&se_dev_1, SE_TZRAM_OPERATION);
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}
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if (timeout == TIMEOUT_100MS) {
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ERROR("%s: ERR: TZRAM save timeout!\n", __func__);
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ret = -ETIMEDOUT;
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}
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if (ret == 0) {
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INFO("%s: SE TZRAM save done!\n", __func__);
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}
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return ret;
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}
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/*
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* The function is invoked by SE resume
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*/
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static void tegra_se_warm_boot_resume(const tegra_se_dev_t *se_dev)
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{
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uint32_t val;
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assert(se_dev);
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/* Lock RNG source to ENTROPY on resume */
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val = DRBG_RO_ENT_IGNORE_MEM_ENABLE |
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DRBG_RO_ENT_SRC_LOCK_ENABLE |
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DRBG_RO_ENT_SRC_ENABLE;
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tegra_se_write_32(se_dev, SE_RNG_SRC_CONFIG_REG_OFFSET, val);
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/* Enable and lock the SE atomic context save setting */
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if (tegra_se_ctx_save_auto_enable(se_dev) != 0) {
|
|
ERROR("%s: ERR: enable SE%d context save auto failed!\n",
|
|
__func__, se_dev->se_num);
|
|
}
|
|
|
|
/* Set a random value to SRK to initialize DRBG */
|
|
tegra_se_generate_srk(se_dev);
|
|
}
|
|
|
|
/*
|
|
* The function is invoked on SC7 resume
|
|
*/
|
|
void tegra_se_resume(void)
|
|
{
|
|
tegra_se_warm_boot_resume(&se_dev_1);
|
|
tegra_se_warm_boot_resume(&se_dev_2);
|
|
}
|