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https://github.com/ARM-software/arm-trusted-firmware.git
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82e73ae703
This patch adds (void) for unused function parameters to fix Rule 2.7 of the MISRA standard. Change-Id: Ibc3f10b3bfe73363383b4c28413ab8d99fbc8c89 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
145 lines
4.2 KiB
C
145 lines
4.2 KiB
C
/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <bl31/interrupt_mgmt.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <context.h>
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#include <denver.h>
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#include <lib/bakery_lock.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <plat/common/platform.h>
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#include <tegra_def.h>
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#include <tegra_private.h>
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static DEFINE_BAKERY_LOCK(tegra_fiq_lock);
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/*******************************************************************************
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* Static variables
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******************************************************************************/
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static uint64_t ns_fiq_handler_addr;
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static uint32_t fiq_handler_active;
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static pcpu_fiq_state_t fiq_state[PLATFORM_CORE_COUNT];
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/*******************************************************************************
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* Handler for FIQ interrupts
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******************************************************************************/
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static uint64_t tegra_fiq_interrupt_handler(uint32_t id,
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uint32_t flags,
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void *handle,
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void *cookie)
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{
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cpu_context_t *ctx = cm_get_context(NON_SECURE);
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el3_state_t *el3state_ctx = get_el3state_ctx(ctx);
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uint32_t cpu = plat_my_core_pos();
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uint32_t irq;
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(void)id;
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(void)flags;
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(void)handle;
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(void)cookie;
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bakery_lock_get(&tegra_fiq_lock);
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/*
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* The FIQ was generated when the execution was in the non-secure
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* world. Save the context registers to start with.
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*/
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cm_el1_sysregs_context_save(NON_SECURE);
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/*
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* Save elr_el3 and spsr_el3 from the saved context, and overwrite
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* the context with the NS fiq_handler_addr and SPSR value.
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*/
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fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3));
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fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3));
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/*
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* Set the new ELR to continue execution in the NS world using the
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* FIQ handler registered earlier.
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*/
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assert(ns_fiq_handler_addr);
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write_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3), (ns_fiq_handler_addr));
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/*
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* Mark this interrupt as complete to avoid a FIQ storm.
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*/
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irq = plat_ic_acknowledge_interrupt();
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if (irq < 1022U) {
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plat_ic_end_of_interrupt(irq);
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}
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bakery_lock_release(&tegra_fiq_lock);
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return 0;
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}
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/*******************************************************************************
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* Setup handler for FIQ interrupts
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******************************************************************************/
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void tegra_fiq_handler_setup(void)
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{
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uint32_t flags;
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int32_t rc;
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/* return if already registered */
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if (fiq_handler_active == 0U) {
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/*
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* Register an interrupt handler for FIQ interrupts generated for
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* NS interrupt sources
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*/
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flags = 0U;
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set_interrupt_rm_flag((flags), (NON_SECURE));
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rc = register_interrupt_type_handler(INTR_TYPE_EL3,
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tegra_fiq_interrupt_handler,
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flags);
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if (rc != 0) {
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panic();
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}
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/* handler is now active */
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fiq_handler_active = 1;
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}
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}
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/*******************************************************************************
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* Validate and store NS world's entrypoint for FIQ interrupts
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******************************************************************************/
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void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint)
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{
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ns_fiq_handler_addr = entrypoint;
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}
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/*******************************************************************************
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* Handler to return the NS EL1/EL0 CPU context
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******************************************************************************/
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int32_t tegra_fiq_get_intr_context(void)
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{
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cpu_context_t *ctx = cm_get_context(NON_SECURE);
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gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx);
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const el1_sys_regs_t *el1state_ctx = get_sysregs_ctx(ctx);
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uint32_t cpu = plat_my_core_pos();
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uint64_t val;
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/*
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* We store the ELR_EL3, SPSR_EL3, SP_EL0 and SP_EL1 registers so
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* that el3_exit() sends these values back to the NS world.
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*/
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write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3));
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write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X1), (fiq_state[cpu].spsr_el3));
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val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0));
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write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val));
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val = read_ctx_reg((el1state_ctx), (uint32_t)(CTX_SP_EL1));
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write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X3), (val));
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return 0;
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}
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