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add403514d
This patch adds CPU core and cluster power down sequences to the CPU specific operations framework introduced in a earlier patch. Cortex-A53, Cortex-A57 and generic AEM sequences have been added. The latter is suitable for the Foundation and Base AEM FVPs. A pointer to each CPU's operations structure is saved in the per-cpu data so that it can be easily accessed during power down seqeunces. An optional platform API has been introduced to allow a platform to disable the Accelerator Coherency Port (ACP) during a cluster power down sequence. The weak definition of this function (plat_disable_acp()) does not take any action. It should be overriden with a strong definition if the ACP is present on a platform. Change-Id: I8d09bd40d2f528a28d2d3f19b77101178778685d
75 lines
2.6 KiB
ArmAsm
75 lines
2.6 KiB
ArmAsm
/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
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(MIDR_PN_MASK << MIDR_PN_SHIFT)
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/*
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* Define the offsets to the fields in cpu_ops structure.
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*/
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.struct 0
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CPU_MIDR: /* cpu_ops midr */
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.space 8
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/* Reset fn is needed in BL at reset vector */
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#if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31)
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CPU_RESET_FUNC: /* cpu_ops reset_func */
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.space 8
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#endif
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#if IMAGE_BL31 /* The power down core and cluster is needed only in BL3-1 */
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CPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */
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.space 8
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CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */
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.space 8
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#endif
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CPU_OPS_SIZE = .
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/*
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* Convenience macro to declare cpu_ops structure.
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* Make sure the structure fields are as per the offsets
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* defined above.
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*/
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.macro declare_cpu_ops _name:req, _midr:req, _noresetfunc = 0
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.section cpu_ops, "a"; .align 3
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.type cpu_ops_\_name, %object
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.quad \_midr
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#if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31)
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.if \_noresetfunc
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.quad 0
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.else
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.quad \_name\()_reset_func
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.endif
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#endif
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#if IMAGE_BL31
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.quad \_name\()_core_pwr_dwn
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.quad \_name\()_cluster_pwr_dwn
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#endif
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.endm
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