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5d21b037e1
This patch adds an additional flag `XLAT_TABLE_NC` which marks the translation tables as Non-cacheable for MMU accesses. Change-Id: I7c28ab87f0ce67da237fadc3627beb6792860fd4 Signed-off-by: Summer Qin <summer.qin@arm.com>
144 lines
5.3 KiB
C
144 lines
5.3 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __XLAT_TABLES_DEFS_H__
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#define __XLAT_TABLES_DEFS_H__
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#include <utils.h>
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/* Miscellaneous MMU related constants */
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#define NUM_2MB_IN_GB (1 << 9)
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#define NUM_4K_IN_2MB (1 << 9)
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#define NUM_GB_IN_4GB (1 << 2)
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#define TWO_MB_SHIFT 21
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#define ONE_GB_SHIFT 30
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#define FOUR_KB_SHIFT 12
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#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT)
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#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT)
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#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT)
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#define INVALID_DESC 0x0
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#define BLOCK_DESC 0x1 /* Table levels 0-2 */
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#define TABLE_DESC 0x3 /* Table levels 0-2 */
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#define PAGE_DESC 0x3 /* Table level 3 */
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#define DESC_MASK 0x3
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#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT
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#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT
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#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT
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#define XN (ULL(1) << 2)
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#define PXN (ULL(1) << 1)
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#define CONT_HINT (ULL(1) << 0)
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#define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52)
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#define NON_GLOBAL (1 << 9)
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#define ACCESS_FLAG (1 << 8)
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#define NSH (0x0 << 6)
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#define OSH (0x2 << 6)
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#define ISH (0x3 << 6)
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#define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000)
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#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT /* 4, 16 or 64 KB */
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#define PAGE_SIZE (1 << PAGE_SIZE_SHIFT)
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#define PAGE_SIZE_MASK (PAGE_SIZE - 1)
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#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0)
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#define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */
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#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT)
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#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */
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#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT)
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#ifdef AARCH32
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#define XLAT_TABLE_LEVEL_MIN 1
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#else
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#define XLAT_TABLE_LEVEL_MIN 0
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#endif /* AARCH32 */
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#define XLAT_TABLE_LEVEL_MAX 3
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/* Values for number of entries in each MMU translation table */
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#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
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#define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT)
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#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1)
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/* Values to convert a memory address to an index into a translation table */
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#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT
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#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
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#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
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#define L0_XLAT_ADDRESS_SHIFT (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
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#define XLAT_ADDR_SHIFT(level) (PAGE_SIZE_SHIFT + \
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((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT))
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#define XLAT_BLOCK_SIZE(level) ((u_register_t)1 << XLAT_ADDR_SHIFT(level))
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/* Mask to get the bits used to index inside a block of a certain level */
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#define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - 1)
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/* Mask to get the address bits common to a block of a certain table level*/
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#define XLAT_ADDR_MASK(level) (~XLAT_BLOCK_MASK(level))
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/*
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* AP[1] bit is ignored by hardware and is
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* treated as if it is One in EL2/EL3
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*/
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#define AP_RO (0x1 << 5)
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#define AP_RW (0x0 << 5)
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#define NS (0x1 << 3)
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#define ATTR_NON_CACHEABLE_INDEX 0x2
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#define ATTR_DEVICE_INDEX 0x1
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#define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0
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#define LOWER_ATTRS(x) (((x) & 0xfff) << 2)
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/* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */
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#define ATTR_NON_CACHEABLE (0x44)
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/* Device-nGnRE */
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#define ATTR_DEVICE (0x4)
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/* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */
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#define ATTR_IWBWA_OWBWA_NTR (0xff)
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#define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3))
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#define ATTR_INDEX_MASK 0x3
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#define ATTR_INDEX_GET(attr) (((attr) >> 2) & ATTR_INDEX_MASK)
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/*
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* Flags to override default values used to program system registers while
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* enabling the MMU.
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*/
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#define DISABLE_DCACHE (1 << 0)
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/*
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* This flag marks the translation tables are Non-cacheable for MMU accesses.
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* If the flag is not specified, by default the tables are cacheable.
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*/
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#define XLAT_TABLE_NC (1 << 1)
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#endif /* __XLAT_TABLES_DEFS_H__ */
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