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d780699b5e
Some GICv3 implementations have provision for power management operations at Redistributor level. This patch introduces and provides place-holders for Redistributor power management. The default implementations are empty stubs, but are weakly bound so as to enable implementation-specific drivers to override them. Change-Id: I4fec1358693d3603ca5dce242a2f7f0e730516d8 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
273 lines
10 KiB
C
273 lines
10 KiB
C
/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __GICV3_H__
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#define __GICV3_H__
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/*******************************************************************************
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* GICv3 miscellaneous definitions
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******************************************************************************/
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/* Interrupt group definitions */
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#define INTR_GROUP1S 0
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#define INTR_GROUP0 1
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#define INTR_GROUP1NS 2
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/* Interrupt IDs reported by the HPPIR and IAR registers */
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#define PENDING_G1S_INTID 1020
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#define PENDING_G1NS_INTID 1021
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/* Constant to categorize LPI interrupt */
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#define MIN_LPI_ID 8192
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/*******************************************************************************
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* GICv3 specific Distributor interface register offsets and constants.
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******************************************************************************/
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#define GICD_STATUSR 0x10
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#define GICD_SETSPI_NSR 0x40
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#define GICD_CLRSPI_NSR 0x48
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#define GICD_SETSPI_SR 0x50
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#define GICD_CLRSPI_SR 0x50
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#define GICD_IGRPMODR 0xd00
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/*
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* GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt id and
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* n >= 32, making the effective offset as 0x6100.
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*/
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#define GICD_IROUTER 0x6000
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#define GICD_PIDR2_GICV3 0xffe8
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#define IGRPMODR_SHIFT 5
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/* GICD_CTLR bit definitions */
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#define CTLR_ENABLE_G1NS_SHIFT 1
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#define CTLR_ENABLE_G1S_SHIFT 2
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#define CTLR_ARE_S_SHIFT 4
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#define CTLR_ARE_NS_SHIFT 5
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#define CTLR_DS_SHIFT 6
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#define CTLR_E1NWF_SHIFT 7
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#define GICD_CTLR_RWP_SHIFT 31
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#define CTLR_ENABLE_G1NS_MASK 0x1
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#define CTLR_ENABLE_G1S_MASK 0x1
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#define CTLR_ARE_S_MASK 0x1
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#define CTLR_ARE_NS_MASK 0x1
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#define CTLR_DS_MASK 0x1
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#define CTLR_E1NWF_MASK 0x1
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#define GICD_CTLR_RWP_MASK 0x1
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#define CTLR_ENABLE_G1NS_BIT (1 << CTLR_ENABLE_G1NS_SHIFT)
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#define CTLR_ENABLE_G1S_BIT (1 << CTLR_ENABLE_G1S_SHIFT)
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#define CTLR_ARE_S_BIT (1 << CTLR_ARE_S_SHIFT)
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#define CTLR_ARE_NS_BIT (1 << CTLR_ARE_NS_SHIFT)
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#define CTLR_DS_BIT (1 << CTLR_DS_SHIFT)
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#define CTLR_E1NWF_BIT (1 << CTLR_E1NWF_SHIFT)
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#define GICD_CTLR_RWP_BIT (1 << GICD_CTLR_RWP_SHIFT)
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/* GICD_IROUTER shifts and masks */
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#define IROUTER_IRM_SHIFT 31
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#define IROUTER_IRM_MASK 0x1
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/*******************************************************************************
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* GICv3 Re-distributor interface registers & constants
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******************************************************************************/
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#define GICR_PCPUBASE_SHIFT 0x11
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#define GICR_SGIBASE_OFFSET (1 << 0x10) /* 64 KB */
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#define GICR_CTLR 0x0
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#define GICR_TYPER 0x08
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#define GICR_WAKER 0x14
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#define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + 0x80)
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#define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + 0x100)
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#define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + 0x180)
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#define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + 0x400)
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#define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + 0xc00)
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#define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + 0xc04)
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#define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + 0xd00)
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/* GICR_CTLR bit definitions */
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#define GICR_CTLR_RWP_SHIFT 3
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#define GICR_CTLR_RWP_MASK 0x1
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#define GICR_CTLR_RWP_BIT (1 << GICR_CTLR_RWP_SHIFT)
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/* GICR_WAKER bit definitions */
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#define WAKER_CA_SHIFT 2
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#define WAKER_PS_SHIFT 1
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#define WAKER_CA_MASK 0x1
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#define WAKER_PS_MASK 0x1
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#define WAKER_CA_BIT (1 << WAKER_CA_SHIFT)
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#define WAKER_PS_BIT (1 << WAKER_PS_SHIFT)
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/* GICR_TYPER bit definitions */
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#define TYPER_AFF_VAL_SHIFT 32
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#define TYPER_PROC_NUM_SHIFT 8
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#define TYPER_LAST_SHIFT 4
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#define TYPER_AFF_VAL_MASK 0xffffffff
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#define TYPER_PROC_NUM_MASK 0xffff
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#define TYPER_LAST_MASK 0x1
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#define TYPER_LAST_BIT (1 << TYPER_LAST_SHIFT)
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/*******************************************************************************
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* GICv3 CPU interface registers & constants
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******************************************************************************/
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/* ICC_SRE bit definitions*/
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#define ICC_SRE_EN_BIT (1 << 3)
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#define ICC_SRE_DIB_BIT (1 << 2)
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#define ICC_SRE_DFB_BIT (1 << 1)
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#define ICC_SRE_SRE_BIT (1 << 0)
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/* ICC_IGRPEN1_EL3 bit definitions */
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#define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0
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#define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1
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#define IGRPEN1_EL3_ENABLE_G1NS_BIT (1 << IGRPEN1_EL3_ENABLE_G1NS_SHIFT)
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#define IGRPEN1_EL3_ENABLE_G1S_BIT (1 << IGRPEN1_EL3_ENABLE_G1S_SHIFT)
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/* ICC_IGRPEN0_EL1 bit definitions */
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#define IGRPEN1_EL1_ENABLE_G0_SHIFT 0
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#define IGRPEN1_EL1_ENABLE_G0_BIT (1 << IGRPEN1_EL1_ENABLE_G0_SHIFT)
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/* ICC_HPPIR0_EL1 bit definitions */
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#define HPPIR0_EL1_INTID_SHIFT 0
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#define HPPIR0_EL1_INTID_MASK 0xffffff
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/* ICC_HPPIR1_EL1 bit definitions */
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#define HPPIR1_EL1_INTID_SHIFT 0
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#define HPPIR1_EL1_INTID_MASK 0xffffff
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/* ICC_IAR0_EL1 bit definitions */
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#define IAR0_EL1_INTID_SHIFT 0
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#define IAR0_EL1_INTID_MASK 0xffffff
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/* ICC_IAR1_EL1 bit definitions */
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#define IAR1_EL1_INTID_SHIFT 0
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#define IAR1_EL1_INTID_MASK 0xffffff
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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#include <types.h>
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#define gicv3_is_intr_id_special_identifier(id) \
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(((id) >= PENDING_G1S_INTID) && ((id) <= GIC_SPURIOUS_INTERRUPT))
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/*******************************************************************************
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* Helper GICv3 macros for SEL1
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******************************************************************************/
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#define gicv3_acknowledge_interrupt_sel1() read_icc_iar1_el1() &\
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IAR1_EL1_INTID_MASK
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#define gicv3_get_pending_interrupt_id_sel1() read_icc_hppir1_el1() &\
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HPPIR1_EL1_INTID_MASK
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#define gicv3_end_of_interrupt_sel1(id) write_icc_eoir1_el1(id)
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/*******************************************************************************
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* Helper GICv3 macros for EL3
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******************************************************************************/
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#define gicv3_acknowledge_interrupt() read_icc_iar0_el1() &\
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IAR0_EL1_INTID_MASK
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#define gicv3_end_of_interrupt(id) write_icc_eoir0_el1(id)
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/*******************************************************************************
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* This structure describes some of the implementation defined attributes of the
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* GICv3 IP. It is used by the platform port to specify these attributes in order
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* to initialise the GICV3 driver. The attributes are described below.
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*
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* 1. The 'gicd_base' field contains the base address of the Distributor
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* interface programmer's view.
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*
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* 2. The 'gicr_base' field contains the base address of the Re-distributor
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* interface programmer's view.
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*
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* 3. The 'g0_interrupt_array' field is a ponter to an array in which each
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* entry corresponds to an ID of a Group 0 interrupt.
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*
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* 4. The 'g0_interrupt_num' field contains the number of entries in the
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* 'g0_interrupt_array'.
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*
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* 5. The 'g1s_interrupt_array' field is a ponter to an array in which each
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* entry corresponds to an ID of a Group 1 interrupt.
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*
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* 6. The 'g1s_interrupt_num' field contains the number of entries in the
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* 'g1s_interrupt_array'.
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*
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* 7. The 'rdistif_num' field contains the number of Redistributor interfaces
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* the GIC implements. This is equal to the number of CPUs or CPU interfaces
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* instantiated in the GIC.
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*
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* 8. The 'rdistif_base_addrs' field is a pointer to an array that has an entry
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* for storing the base address of the Redistributor interface frame of each
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* CPU in the system. The size of the array = 'rdistif_num'. The base
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* addresses are detected during driver initialisation.
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*
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* 9. The 'mpidr_to_core_pos' field is a pointer to a hash function which the
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* driver will use to convert an MPIDR value to a linear core index. This
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* index will be used for accessing the 'rdistif_base_addrs' array. This is
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* an optional field. A GICv3 implementation maps each MPIDR to a linear core
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* index as well. This mapping can be found by reading the "Affinity Value"
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* and "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the
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* "Processor Numbers" are suitable to index into an array to access core
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* specific information. If this not the case, the platform port must provide
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* a hash function. Otherwise, the "Processor Number" field will be used to
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* access the array elements.
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******************************************************************************/
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typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr);
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typedef struct gicv3_driver_data {
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uintptr_t gicd_base;
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uintptr_t gicr_base;
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unsigned int g0_interrupt_num;
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unsigned int g1s_interrupt_num;
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const unsigned int *g0_interrupt_array;
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const unsigned int *g1s_interrupt_array;
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unsigned int rdistif_num;
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uintptr_t *rdistif_base_addrs;
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mpidr_hash_fn mpidr_to_core_pos;
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} gicv3_driver_data_t;
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/*******************************************************************************
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* GICv3 EL3 driver API
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******************************************************************************/
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void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data);
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void gicv3_distif_init(void);
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void gicv3_rdistif_init(unsigned int proc_num);
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void gicv3_rdistif_on(unsigned int proc_num);
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void gicv3_rdistif_off(unsigned int proc_num);
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void gicv3_cpuif_enable(unsigned int proc_num);
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void gicv3_cpuif_disable(unsigned int proc_num);
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unsigned int gicv3_get_pending_interrupt_type(void);
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unsigned int gicv3_get_pending_interrupt_id(void);
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unsigned int gicv3_get_interrupt_type(unsigned int id,
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unsigned int proc_num);
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#endif /* __ASSEMBLY__ */
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#endif /* __GICV3_H__ */
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