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https://github.com/ARM-software/arm-trusted-firmware.git
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ac9f4b4da6
The erratum titled “Disabling of data prefetcher with outstanding prefetch TLB miss might cause a deadlock” should not be handled within TF-A. The current workaround attempts to follow option 2 but misapplies it. Specifically, it statically sets PF_MODE to conservative, which is not the recommended approach. According to the erratum documentation, PF_MODE should be configured in conservative mode only when we disable data prefetcher however this is not done in TF-A and thus the workaround is not needed in TF-A. The static setting of PF_MODE in TF-A does not correctly address the erratum and may introduce unnecessary performance degradation on platforms that adopt it without fully understanding its implications. To prevent incorrect or unintended use, the current implementation of this erratum workaround should be removed from TF-A and not adopted by platforms. List of Impacted CPU's with Errata Numbers and reference to SDEN - Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
128 lines
3.8 KiB
Makefile
128 lines
3.8 KiB
Makefile
#
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# Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
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# Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# Make for SC7280 QTI platform.
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QTI_PLAT_PATH := plat/qti
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CHIPSET := ${PLAT}
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# Turn On Separate code & data.
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SEPARATE_CODE_AND_RODATA := 1
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USE_COHERENT_MEM := 0
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WARMBOOT_ENABLE_DCACHE_EARLY := 1
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HW_ASSISTED_COHERENCY := 1
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#Enable errata configs for cortex_a78 and cortex_a55
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ERRATA_A55_1530923 := 1
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ERRATA_A78_1941498 := 1
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ERRATA_A78_1951500 := 1
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# Disable the PSCI platform compatibility layer
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ENABLE_PLAT_COMPAT := 0
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# Enable PSCI v1.0 extended state ID format
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PSCI_EXTENDED_STATE_ID := 1
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ARM_RECOM_STATE_ID_ENC := 1
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PSCI_OS_INIT_MODE := 1
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COLD_BOOT_SINGLE_CPU := 1
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PROGRAMMABLE_RESET_ADDRESS := 1
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RESET_TO_BL31 := 0
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QTI_SDI_BUILD := 0
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$(eval $(call assert_boolean,QTI_SDI_BUILD))
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$(eval $(call add_define,QTI_SDI_BUILD))
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#disable CTX_INCLUDE_AARCH32_REGS to support sc7280 gold cores
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override CTX_INCLUDE_AARCH32_REGS := 0
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WORKAROUND_CVE_2017_5715 := 0
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DYNAMIC_WORKAROUND_CVE_2018_3639 := 1
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# Enable stack protector.
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ENABLE_STACK_PROTECTOR := strong
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QTI_EXTERNAL_INCLUDES := -I${QTI_PLAT_PATH}/${CHIPSET}/inc \
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-I${QTI_PLAT_PATH}/common/inc \
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-I${QTI_PLAT_PATH}/common/inc/$(ARCH) \
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-I${QTI_PLAT_PATH}/qtiseclib/inc \
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-I${QTI_PLAT_PATH}/qtiseclib/inc/${CHIPSET} \
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QTI_BL31_SOURCES := $(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_helpers.S \
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$(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_kryo6_silver.S \
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$(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_kryo6_gold.S \
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$(QTI_PLAT_PATH)/common/src/$(ARCH)/qti_uart_console.S \
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$(QTI_PLAT_PATH)/common/src/pm_ps_hold.c \
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$(QTI_PLAT_PATH)/common/src/qti_stack_protector.c \
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$(QTI_PLAT_PATH)/common/src/qti_common.c \
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$(QTI_PLAT_PATH)/common/src/qti_bl31_setup.c \
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$(QTI_PLAT_PATH)/common/src/qti_gic_v3.c \
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$(QTI_PLAT_PATH)/common/src/qti_interrupt_svc.c \
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$(QTI_PLAT_PATH)/common/src/qti_syscall.c \
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$(QTI_PLAT_PATH)/common/src/qti_topology.c \
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$(QTI_PLAT_PATH)/common/src/qti_pm.c \
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$(QTI_PLAT_PATH)/common/src/qti_rng.c \
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$(QTI_PLAT_PATH)/common/src/spmi_arb.c \
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$(QTI_PLAT_PATH)/qtiseclib/src/qtiseclib_cb_interface.c \
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PLAT_INCLUDES := -Iinclude/plat/common/ \
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PLAT_INCLUDES += ${QTI_EXTERNAL_INCLUDES}
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include lib/xlat_tables_v2/xlat_tables.mk
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PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} \
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plat/common/aarch64/crash_console_helpers.S \
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common/desc_image_load.c \
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lib/bl_aux_params/bl_aux_params.c \
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include lib/coreboot/coreboot.mk
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#PSCI Sources.
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PSCI_SOURCES := plat/common/plat_psci_common.c \
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# GIC-600 configuration
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GICV3_SUPPORT_GIC600 := 1
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# Include GICv3 driver files
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include drivers/arm/gic/v3/gicv3.mk
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#Timer sources
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TIMER_SOURCES := drivers/delay_timer/generic_delay_timer.c \
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drivers/delay_timer/delay_timer.c \
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#GIC sources.
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GIC_SOURCES := plat/common/plat_gicv3.c \
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${GICV3_SOURCES} \
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CPU_SOURCES := lib/cpus/aarch64/cortex_a78.S \
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lib/cpus/aarch64/cortex_a55.S \
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BL31_SOURCES += ${QTI_BL31_SOURCES} \
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${PSCI_SOURCES} \
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${GIC_SOURCES} \
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${TIMER_SOURCES} \
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${CPU_SOURCES} \
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LIB_QTI_PATH := ${QTI_PLAT_PATH}/qtiseclib/lib/${CHIPSET}
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# Override this on the command line to point to the qtiseclib library which
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# will be available in coreboot.org
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QTISECLIB_PATH ?=
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ifeq ($(QTISECLIB_PATH),)
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# if No lib then use stub implementation for qtiseclib interface
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$(warning QTISECLIB_PATH is not provided while building, using stub implementation. \
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Please refer docs/plat/qti.rst for more details \
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THIS FIRMWARE WILL NOT BOOT!)
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BL31_SOURCES += plat/qti/qtiseclib/src/qtiseclib_interface_stub.c
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else
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# use library provided by QTISECLIB_PATH
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LDFLAGS += -L $(dir $(QTISECLIB_PATH))
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LDLIBS += -l$(patsubst lib%.a,%,$(notdir $(QTISECLIB_PATH)))
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endif
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