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ac9f4b4da6
The erratum titled “Disabling of data prefetcher with outstanding prefetch TLB miss might cause a deadlock” should not be handled within TF-A. The current workaround attempts to follow option 2 but misapplies it. Specifically, it statically sets PF_MODE to conservative, which is not the recommended approach. According to the erratum documentation, PF_MODE should be configured in conservative mode only when we disable data prefetcher however this is not done in TF-A and thus the workaround is not needed in TF-A. The static setting of PF_MODE in TF-A does not correctly address the erratum and may introduce unnecessary performance degradation on platforms that adopt it without fully understanding its implications. To prevent incorrect or unintended use, the current implementation of this erratum workaround should be removed from TF-A and not adopted by platforms. List of Impacted CPU's with Errata Numbers and reference to SDEN - Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
157 lines
5.6 KiB
ArmAsm
157 lines
5.6 KiB
ArmAsm
/*
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* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <neoverse_v2.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse V2 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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cpu_reset_prologue neoverse_v2
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workaround_reset_start neoverse_v2, ERRATUM(2618597), ERRATA_V2_2618597
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/* Disable retention control for WFI and WFE. */
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mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1
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bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT, \
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#NEOVERSE_V2_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH
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bfi x0, xzr, #NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT, \
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#NEOVERSE_V2_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH
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msr NEOVERSE_V2_CPUPWRCTLR_EL1, x0
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workaround_reset_end neoverse_v2, ERRATUM(2618597)
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check_erratum_ls neoverse_v2, ERRATUM(2618597), CPU_REV(0, 1)
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workaround_reset_start neoverse_v2, ERRATUM(2662553), ERRATA_V2_2662553
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sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL, \
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NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB, NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH
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workaround_reset_end neoverse_v2, ERRATUM(2662553)
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check_erratum_ls neoverse_v2, ERRATUM(2662553), CPU_REV(0, 1)
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workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105
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sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0
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workaround_reset_end neoverse_v2, ERRATUM(2719105)
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check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1)
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workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011
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sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_55
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sysreg_bit_clear NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_56
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workaround_reset_end neoverse_v2, ERRATUM(2743011)
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check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1)
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workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510
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sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47
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workaround_reset_end neoverse_v2, ERRATUM(2779510)
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check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1)
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workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
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/* dsb before isb of power down sequence */
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dsb sy
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workaround_runtime_end neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
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check_erratum_ls neoverse_v2, ERRATUM(2801372), CPU_REV(0, 1)
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workaround_reset_start neoverse_v2, CVE(2022,23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Neoverse-V2 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_neoverse_v2
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#endif /* IMAGE_BL31 */
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workaround_reset_end neoverse_v2, CVE(2022,23960)
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check_erratum_chosen neoverse_v2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start neoverse_v2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, BIT(46)
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workaround_reset_end neoverse_v2, CVE(2024, 5660)
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check_erratum_ls neoverse_v2, CVE(2024, 5660), CPU_REV(0, 2)
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table NEOVERSE_V2_BHB_LOOP_COUNT, neoverse_v2
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#endif /* WORKAROUND_CVE_2022_23960 */
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workaround_reset_start neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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/* ---------------------------------
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* Sets BIT41 of CPUACTLR6_EL1 which
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* disables L1 Data cache prefetcher
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* ---------------------------------
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*/
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sysreg_bit_set NEOVERSE_V2_CPUACTLR6_EL1, BIT(41)
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workaround_reset_end neoverse_v2, CVE(2024, 7881)
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check_erratum_chosen neoverse_v2, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func neoverse_v2_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set NEOVERSE_V2_CPUPWRCTLR_EL1, NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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apply_erratum neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372, NO_GET_CPU_REV
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isb
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ret
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endfunc neoverse_v2_core_pwr_dwn
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cpu_reset_func_start neoverse_v2
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/* Disable speculative loads */
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msr SSBS, xzr
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#if NEOVERSE_Vx_EXTERNAL_LLC
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/* Some systems may have External LLC, core needs to be made aware */
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sysreg_bit_set NEOVERSE_V2_CPUECTLR_EL1, NEOVERSE_V2_CPUECTLR_EL1_EXTLLC_BIT
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#endif
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cpu_reset_func_end neoverse_v2
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/* ---------------------------------------------
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* This function provides Neoverse V2-
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* specific register information for crash
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* reporting. It needs to return with x6
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* pointing to a list of register names in ascii
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* and x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.neoverse_v2_regs, "aS"
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neoverse_v2_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func neoverse_v2_cpu_reg_dump
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adr x6, neoverse_v2_regs
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mrs x8, NEOVERSE_V2_CPUECTLR_EL1
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ret
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endfunc neoverse_v2_cpu_reg_dump
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declare_cpu_ops_wa_4 neoverse_v2, NEOVERSE_V2_MIDR, \
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neoverse_v2_reset_func, \
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CPU_NO_EXTRA1_FUNC, \
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CPU_NO_EXTRA2_FUNC, \
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CPU_NO_EXTRA3_FUNC, \
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check_erratum_neoverse_v2_7881, \
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neoverse_v2_core_pwr_dwn
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