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ac9f4b4da6
The erratum titled “Disabling of data prefetcher with outstanding prefetch TLB miss might cause a deadlock” should not be handled within TF-A. The current workaround attempts to follow option 2 but misapplies it. Specifically, it statically sets PF_MODE to conservative, which is not the recommended approach. According to the erratum documentation, PF_MODE should be configured in conservative mode only when we disable data prefetcher however this is not done in TF-A and thus the workaround is not needed in TF-A. The static setting of PF_MODE in TF-A does not correctly address the erratum and may introduce unnecessary performance degradation on platforms that adopt it without fully understanding its implications. To prevent incorrect or unintended use, the current implementation of this erratum workaround should be removed from TF-A and not adopted by platforms. List of Impacted CPU's with Errata Numbers and reference to SDEN - Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
314 lines
11 KiB
ArmAsm
314 lines
11 KiB
ArmAsm
/*
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* Copyright (c) 2020-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpu_macros.S>
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#include <dsu_macros.S>
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#include <neoverse_n2.h>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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.global check_erratum_neoverse_n2_3701773
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2
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#endif /* WORKAROUND_CVE_2022_23960 */
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cpu_reset_prologue neoverse_n2
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workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655
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/* Apply instruction patching sequence */
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ldr x0,=0x6
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xF3A08002
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFF0F7FE
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x40000001003ff
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msr S3_6_c15_c8_1,x0
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ldr x0,=0x7
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xBF200000
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFEF0000
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x40000001003f3
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msr S3_6_c15_c8_1,x0
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workaround_reset_end neoverse_n2, ERRATUM(2002655)
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check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0)
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workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478
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/* Stash ERRSELR_EL1 in x2 */
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mrs x2, ERRSELR_EL1
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/* Select error record 0 and clear ED bit */
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msr ERRSELR_EL1, xzr
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mrs x1, ERXCTLR_EL1
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bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
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msr ERXCTLR_EL1, x1
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/* Restore ERRSELR_EL1 from x2 */
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msr ERRSELR_EL1, x2
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workaround_runtime_end neoverse_n2, ERRATUM(2009478), NO_ISB
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check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414
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sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
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workaround_reset_end neoverse_n2, ERRATUM(2025414)
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check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956
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sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
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workaround_reset_end neoverse_n2, ERRATUM(2067956)
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check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956
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/* Apply instruction patching sequence */
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ldr x0,=0x3
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xF3A08002
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFF0F7FE
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x10002001003FF
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msr S3_6_c15_c8_1,x0
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ldr x0,=0x4
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msr S3_6_c15_c8_0,x0
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ldr x0,=0xBF200000
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msr S3_6_c15_c8_2,x0
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ldr x0,=0xFFEF0000
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msr S3_6_c15_c8_3,x0
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ldr x0,=0x10002001003F3
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msr S3_6_c15_c8_1,x0
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workaround_reset_end neoverse_n2, ERRATUM(2138956)
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check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958
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/* Apply instruction patching sequence */
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sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13
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workaround_reset_end neoverse_n2, ERRATUM(2138958)
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check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731
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sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44
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workaround_reset_end neoverse_n2, ERRATUM(2189731)
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check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400
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/* Apply instruction patching sequence */
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sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17
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ldr x0, =0x2
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msr S3_6_c15_c8_0, x0
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ldr x0, =0x10F600E000
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msr S3_6_c15_c8_2, x0
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ldr x0, =0x10FF80E000
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msr S3_6_c15_c8_3, x0
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ldr x0, =0x80000000003FF
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msr S3_6_c15_c8_1, x0
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workaround_reset_end neoverse_n2, ERRATUM(2242400)
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check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415
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sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
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workaround_reset_end neoverse_n2, ERRATUM(2242415)
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check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757
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/* Apply instruction patching sequence */
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sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
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workaround_reset_end neoverse_n2, ERRATUM(2280757)
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check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941
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errata_dsu_2313941_wa_impl
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workaround_reset_end neoverse_n2, ERRATUM(2313941)
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check_erratum_custom_start neoverse_n2, ERRATUM(2313941)
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branch_if_scu_not_present 2f /* label 1 is used in the macro */
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check_errata_dsu_2313941_impl
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2:
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ret
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check_erratum_custom_end neoverse_n2, ERRATUM(2313941)
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.global erratum_neoverse_n2_2326639_wa
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workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639
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/* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying
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* the workaround. Second call clears it to undo it. */
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sysreg_bit_toggle NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36
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workaround_runtime_end neoverse_n2, ERRATUM(2326639)
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check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2340933), ERRATA_N2_2340933
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/* Set bit 61 in CPUACTLR5_EL1 */
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sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, BIT(61)
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workaround_reset_end neoverse_n2, ERRATUM(2340933)
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check_erratum_ls neoverse_n2, ERRATUM(2340933), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2346952), ERRATA_N2_2346952
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/* Set TXREQ to STATIC and full L2 TQ size */
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mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
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mov x0, #CPUECTLR2_EL1_TXREQ_STATIC_FULL
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bfi x1, x0, #CPUECTLR2_EL1_TXREQ_LSB, #CPUECTLR2_EL1_TXREQ_WIDTH
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msr NEOVERSE_N2_CPUECTLR2_EL1, x1
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workaround_reset_end neoverse_n2, ERRATUM(2346952)
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check_erratum_ls neoverse_n2, ERRATUM(2346952), CPU_REV(0, 2)
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workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738
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/* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM
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* ST to behave like PLD/PFRM LD and not cause
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* invalidations to other PE caches.
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*/
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sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0
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workaround_reset_end neoverse_n2, ERRATUM(2376738)
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check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 3)
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workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450
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/*Set bit 40 in ACTLR2_EL1 */
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sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40
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workaround_reset_end neoverse_n2, ERRATUM(2388450)
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check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0)
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workaround_reset_start neoverse_n2, ERRATUM(2743014), ERRATA_N2_2743014
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/* Set CPUACTLR5_EL1[56:55] to 2'b01 */
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sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_55
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sysreg_bit_clear NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_56
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workaround_reset_end neoverse_n2, ERRATUM(2743014)
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check_erratum_ls neoverse_n2, ERRATUM(2743014), CPU_REV(0, 2)
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workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089
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/* dsb before isb of power down sequence */
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dsb sy
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workaround_runtime_end neoverse_n2, ERRATUM(2743089)
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check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2)
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workaround_reset_start neoverse_n2, ERRATUM(2779511), ERRATA_N2_2779511
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/* Set bit 47 in ACTLR3_EL1 */
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sysreg_bit_set NEOVERSE_N2_CPUACTLR3_EL1, NEOVERSE_N2_CPUACTLR3_EL1_BIT_47
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workaround_reset_end neoverse_n2, ERRATUM(2779511)
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check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2)
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add_erratum_entry neoverse_n2, ERRATUM(3701773), ERRATA_N2_3701773
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check_erratum_ls neoverse_n2, ERRATUM(3701773), CPU_REV(0, 3)
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workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Neoverse-N2 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_neoverse_n2
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#endif /* IMAGE_BL31 */
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workaround_reset_end neoverse_n2, CVE(2022,23960)
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check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start neoverse_n2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, BIT(46)
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workaround_reset_end neoverse_n2, CVE(2024, 5660)
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check_erratum_ls neoverse_n2, CVE(2024, 5660), CPU_REV(0, 3)
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/* -------------------------------------------
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* The CPU Ops reset function for Neoverse N2.
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* -------------------------------------------
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*/
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cpu_reset_func_start neoverse_n2
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/* Check if the PE implements SSBS */
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mrs x0, id_aa64pfr1_el1
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tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
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b.eq 1f
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/* Disable speculative loads */
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msr SSBS, xzr
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1:
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/* Force all cacheable atomic instructions to be near */
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sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2
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#if ENABLE_FEAT_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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sysreg_bit_clear cptr_el3, TAM_BIT
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/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
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sysreg_bit_clear cptr_el2, TAM_BIT
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/* No need to enable the counters as this would be done at el3 exit */
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#endif
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#if NEOVERSE_Nx_EXTERNAL_LLC
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/* Some systems may have External LLC, core needs to be made aware */
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sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
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#endif
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cpu_reset_func_end neoverse_n2
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func neoverse_n2_core_pwr_dwn
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apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478, NO_GET_CPU_REV
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apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* No need to do cache maintenance here.
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* ---------------------------------------------------
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*/
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sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT
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apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089, NO_GET_CPU_REV
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isb
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ret
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endfunc neoverse_n2_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides Neoverse N2 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ASCII and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.neoverse_n2_regs, "aS"
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neoverse_n2_regs: /* The ASCII list of register names to be reported */
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.asciz "cpupwrctlr_el1", ""
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func neoverse_n2_cpu_reg_dump
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adr x6, neoverse_n2_regs
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mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1
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ret
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endfunc neoverse_n2_cpu_reg_dump
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declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \
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neoverse_n2_reset_func, \
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neoverse_n2_core_pwr_dwn
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