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ac9f4b4da6
The erratum titled “Disabling of data prefetcher with outstanding prefetch TLB miss might cause a deadlock” should not be handled within TF-A. The current workaround attempts to follow option 2 but misapplies it. Specifically, it statically sets PF_MODE to conservative, which is not the recommended approach. According to the erratum documentation, PF_MODE should be configured in conservative mode only when we disable data prefetcher however this is not done in TF-A and thus the workaround is not needed in TF-A. The static setting of PF_MODE in TF-A does not correctly address the erratum and may introduce unnecessary performance degradation on platforms that adopt it without fully understanding its implications. To prevent incorrect or unintended use, the current implementation of this erratum workaround should be removed from TF-A and not adopted by platforms. List of Impacted CPU's with Errata Numbers and reference to SDEN - Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
176 lines
6.1 KiB
ArmAsm
176 lines
6.1 KiB
ArmAsm
/*
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* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_x3.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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.global check_erratum_cortex_x3_3701769
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3
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#endif /* WORKAROUND_CVE_2022_23960 */
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cpu_reset_prologue cortex_x3
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workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875
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sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22)
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workaround_reset_end cortex_x3, ERRATUM(2266875)
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check_erratum_ls cortex_x3, ERRATUM(2266875), CPU_REV(1, 0)
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workaround_reset_start cortex_x3, ERRATUM(2302506), ERRATA_X3_2302506
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sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(0)
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workaround_reset_end cortex_x3, ERRATUM(2302506)
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check_erratum_ls cortex_x3, ERRATUM(2302506), CPU_REV(1, 1)
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.global erratum_cortex_x3_2313909_wa
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workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
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/* Set/unset bit 36 in ACTLR2_EL1. The first call will set it, applying
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* the workaround. Second call clears it to undo it. */
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sysreg_bit_toggle CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36
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workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB
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check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0)
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workaround_reset_start cortex_x3, ERRATUM(2372204), ERRATA_X3_2372204
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/* Set bit 40 in CPUACTLR2_EL1 */
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sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, BIT(40)
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workaround_reset_end cortex_x3, ERRATUM(2372204)
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check_erratum_ls cortex_x3, ERRATUM(2372204), CPU_REV(1, 0)
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workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812
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/* Disable retention control for WFI and WFE. */
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mrs x0, CORTEX_X3_CPUPWRCTLR_EL1
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bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3
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bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3
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msr CORTEX_X3_CPUPWRCTLR_EL1, x0
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workaround_reset_end cortex_x3, ERRATUM(2615812)
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check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1)
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workaround_reset_start cortex_x3, ERRATUM(2641945), ERRATA_X3_2641945
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sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41)
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workaround_reset_end cortex_x3, ERRATUM(2641945)
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check_erratum_ls cortex_x3, ERRATUM(2641945), CPU_REV(1, 0)
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workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421
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/* Set CPUACTLR5_EL1[56:55] to 2'b01 */
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sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55
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sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56
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workaround_reset_end cortex_x3, ERRATUM(2742421)
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check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1)
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workaround_runtime_start cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088
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/* dsb before isb of power down sequence */
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dsb sy
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workaround_runtime_end cortex_x3, ERRATUM(2743088), NO_ISB
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check_erratum_ls cortex_x3, ERRATUM(2743088), CPU_REV(1, 1)
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workaround_reset_start cortex_x3, ERRATUM(2779509), ERRATA_X3_2779509
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/* Set CPUACTLR3_EL1 bit 47 */
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sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47
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workaround_reset_end cortex_x3, ERRATUM(2779509)
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check_erratum_ls cortex_x3, ERRATUM(2779509), CPU_REV(1, 1)
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add_erratum_entry cortex_x3, ERRATUM(3701769), ERRATA_X3_3701769
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check_erratum_ls cortex_x3, ERRATUM(3701769), CPU_REV(1, 2)
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workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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override_vector_table wa_cve_vbar_cortex_x3
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_x3, CVE(2022, 23960)
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check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_x3, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_X3_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_x3, CVE(2024, 5660)
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check_erratum_ls cortex_x3, CVE(2024, 5660), CPU_REV(1, 2)
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workaround_reset_start cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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/* ---------------------------------
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* Sets BIT41 of CPUACTLR6_EL1 which
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* disables L1 Data cache prefetcher
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* ---------------------------------
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*/
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sysreg_bit_set CORTEX_X3_CPUACTLR6_EL1, BIT(41)
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workaround_reset_end cortex_x3, CVE(2024, 7881)
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check_erratum_chosen cortex_x3, CVE(2024, 7881), WORKAROUND_CVE_2024_7881
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cpu_reset_func_start cortex_x3
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/* Disable speculative loads */
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msr SSBS, xzr
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enable_mpmm
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cpu_reset_func_end cortex_x3
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_x3_core_pwr_dwn
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apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909, NO_GET_CPU_REV
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088, NO_GET_CPU_REV
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isb
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ret
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endfunc cortex_x3_core_pwr_dwn
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/* ---------------------------------------------
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* This function provides Cortex-X3-
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* specific register information for crash
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* reporting. It needs to return with x6
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* pointing to a list of register names in ascii
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* and x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_x3_regs, "aS"
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cortex_x3_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_x3_cpu_reg_dump
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adr x6, cortex_x3_regs
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mrs x8, CORTEX_X3_CPUECTLR_EL1
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ret
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endfunc cortex_x3_cpu_reg_dump
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declare_cpu_ops_wa_4 cortex_x3, CORTEX_X3_MIDR, \
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cortex_x3_reset_func, \
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CPU_NO_EXTRA1_FUNC, \
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CPU_NO_EXTRA2_FUNC, \
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CPU_NO_EXTRA3_FUNC, \
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check_erratum_cortex_x3_7881, \
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cortex_x3_core_pwr_dwn
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