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ac9f4b4da6
The erratum titled “Disabling of data prefetcher with outstanding prefetch TLB miss might cause a deadlock” should not be handled within TF-A. The current workaround attempts to follow option 2 but misapplies it. Specifically, it statically sets PF_MODE to conservative, which is not the recommended approach. According to the erratum documentation, PF_MODE should be configured in conservative mode only when we disable data prefetcher however this is not done in TF-A and thus the workaround is not needed in TF-A. The static setting of PF_MODE in TF-A does not correctly address the erratum and may introduce unnecessary performance degradation on platforms that adopt it without fully understanding its implications. To prevent incorrect or unintended use, the current implementation of this erratum workaround should be removed from TF-A and not adopted by platforms. List of Impacted CPU's with Errata Numbers and reference to SDEN - Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
215 lines
7 KiB
ArmAsm
215 lines
7 KiB
ArmAsm
/*
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* Copyright (c) 2021-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_x2.h>
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#include <cpu_macros.S>
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#include <dsu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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.global check_erratum_cortex_x2_3701772
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2
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#endif /* WORKAROUND_CVE_2022_23960 */
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cpu_reset_prologue cortex_x2
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workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765
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ldr x0, =0x6
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msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
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ldr x0, =0xF3A08002
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msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */
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ldr x0, =0xFFF0F7FE
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msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */
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ldr x0, =0x40000001003ff
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msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */
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workaround_reset_end cortex_x2, ERRATUM(2002765)
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check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0)
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workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096
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sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT
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workaround_reset_end cortex_x2, ERRATUM(2017096)
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check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0)
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workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180
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/* Apply instruction patching sequence */
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ldr x0, =0x3
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msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
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ldr x0, =0xF3A08002
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msr CORTEX_X2_IMP_CPUPOR_EL3, x0
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ldr x0, =0xFFF0F7FE
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msr CORTEX_X2_IMP_CPUPMR_EL3, x0
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ldr x0, =0x10002001003FF
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msr CORTEX_X2_IMP_CPUPCR_EL3, x0
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ldr x0, =0x4
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msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
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ldr x0, =0xBF200000
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msr CORTEX_X2_IMP_CPUPOR_EL3, x0
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ldr x0, =0xFFEF0000
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msr CORTEX_X2_IMP_CPUPMR_EL3, x0
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ldr x0, =0x10002001003F3
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msr CORTEX_X2_IMP_CPUPCR_EL3, x0
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workaround_reset_end cortex_x2, ERRATUM(2081180)
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check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0)
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workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908
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/* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */
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sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13)
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workaround_reset_end cortex_x2, ERRATUM(2083908)
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check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0)
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workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715
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/* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */
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sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22
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workaround_reset_end cortex_x2, ERRATUM(2147715)
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check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0)
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workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384
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sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17
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/* Apply instruction patching sequence */
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ldr x0, =0x5
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msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
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ldr x0, =0x10F600E000
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msr CORTEX_X2_IMP_CPUPOR_EL3, x0
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ldr x0, =0x10FF80E000
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msr CORTEX_X2_IMP_CPUPMR_EL3, x0
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ldr x0, =0x80000000003FF
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msr CORTEX_X2_IMP_CPUPCR_EL3, x0
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workaround_reset_end cortex_x2, ERRATUM(2216384)
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check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0)
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workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622
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/* Apply the workaround */
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sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0)
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workaround_reset_end cortex_x2, ERRATUM(2282622)
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check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1)
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workaround_reset_start cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941
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errata_dsu_2313941_wa_impl
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workaround_reset_end cortex_x2, ERRATUM(2313941)
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check_erratum_custom_start cortex_x2, ERRATUM(2313941)
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check_errata_dsu_2313941_impl
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ret
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check_erratum_custom_end cortex_x2, ERRATUM(2313941)
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workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105
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/* Set bit 40 in CPUACTLR2_EL1 */
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sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40
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workaround_reset_end cortex_x2, ERRATUM(2371105)
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check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0)
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workaround_reset_start cortex_x2, ERRATUM(2742423), ERRATA_X2_2742423
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/* Set CPUACTLR5_EL1[56:55] to 2'b01 */
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sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(55)
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sysreg_bit_clear CORTEX_X2_CPUACTLR5_EL1, BIT(56)
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workaround_reset_end cortex_x2, ERRATUM(2742423)
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check_erratum_ls cortex_x2, ERRATUM(2742423), CPU_REV(2, 1)
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workaround_runtime_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515
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/* dsb before isb of power down sequence */
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dsb sy
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workaround_runtime_end cortex_x2, ERRATUM(2768515)
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check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1)
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workaround_reset_start cortex_x2, ERRATUM(2778471), ERRATA_X2_2778471
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sysreg_bit_set CORTEX_X2_CPUACTLR3_EL1, BIT(47)
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workaround_reset_end cortex_x2, ERRATUM(2778471)
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check_erratum_ls cortex_x2, ERRATUM(2778471), CPU_REV(2, 1)
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add_erratum_entry cortex_x2, ERRATUM(3701772), ERRATA_X2_3701772
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check_erratum_ls cortex_x2, ERRATUM(3701772), CPU_REV(2, 1)
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workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Cortex-X2 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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override_vector_table wa_cve_vbar_cortex_x2
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_x2, CVE(2022, 23960)
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check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */
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workaround_reset_start cortex_x2, CVE(2024, 5660), WORKAROUND_CVE_2024_5660
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sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, BIT(46)
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workaround_reset_end cortex_x2, CVE(2024, 5660)
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check_erratum_ls cortex_x2, CVE(2024, 5660), CPU_REV(2, 1)
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_x2_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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apply_erratum cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515, NO_GET_CPU_REV
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isb
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ret
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endfunc cortex_x2_core_pwr_dwn
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cpu_reset_func_start cortex_x2
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/* Disable speculative loads */
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msr SSBS, xzr
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enable_mpmm
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cpu_reset_func_end cortex_x2
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/* ---------------------------------------------
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* This function provides Cortex X2 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_x2_regs, "aS"
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cortex_x2_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_x2_cpu_reg_dump
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adr x6, cortex_x2_regs
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mrs x8, CORTEX_X2_CPUECTLR_EL1
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ret
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endfunc cortex_x2_cpu_reg_dump
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declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \
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cortex_x2_reset_func, \
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cortex_x2_core_pwr_dwn
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