mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-11 07:04:22 +00:00
ac9f4b4da6
The erratum titled “Disabling of data prefetcher with outstanding prefetch TLB miss might cause a deadlock” should not be handled within TF-A. The current workaround attempts to follow option 2 but misapplies it. Specifically, it statically sets PF_MODE to conservative, which is not the recommended approach. According to the erratum documentation, PF_MODE should be configured in conservative mode only when we disable data prefetcher however this is not done in TF-A and thus the workaround is not needed in TF-A. The static setting of PF_MODE in TF-A does not correctly address the erratum and may introduce unnecessary performance degradation on platforms that adopt it without fully understanding its implications. To prevent incorrect or unintended use, the current implementation of this erratum workaround should be removed from TF-A and not adopted by platforms. List of Impacted CPU's with Errata Numbers and reference to SDEN - Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
49 lines
2 KiB
C
49 lines
2 KiB
C
/*
|
|
* Copyright (c) 2019-2025, Arm Limited. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#ifndef NEOVERSE_V1_H
|
|
#define NEOVERSE_V1_H
|
|
|
|
#define NEOVERSE_V1_MIDR U(0x410FD400)
|
|
|
|
/* Neoverse V1 loop count for CVE-2022-23960 mitigation */
|
|
#define NEOVERSE_V1_BHB_LOOP_COUNT U(32)
|
|
|
|
/*******************************************************************************
|
|
* CPU Extended Control register specific definitions.
|
|
******************************************************************************/
|
|
#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4
|
|
#define NEOVERSE_V1_CPUPSELR_EL3 S3_6_C15_C8_0
|
|
#define NEOVERSE_V1_CPUPOR_EL3 S3_6_C15_C8_2
|
|
#define NEOVERSE_V1_CPUPMR_EL3 S3_6_C15_C8_3
|
|
#define NEOVERSE_V1_CPUPCR_EL3 S3_6_C15_C8_1
|
|
#define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
|
|
#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
|
|
|
|
/*******************************************************************************
|
|
* CPU Power Control register specific definitions
|
|
******************************************************************************/
|
|
#define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
|
|
#define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
|
|
|
|
/*******************************************************************************
|
|
* CPU Auxiliary Control register specific definitions.
|
|
******************************************************************************/
|
|
#define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1
|
|
#define NEOVERSE_V1_ACTLR2_EL1_BIT_0 ULL(1)
|
|
#define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
|
|
#define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28)
|
|
#define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
|
|
|
|
#define NEOVERSE_V1_ACTLR3_EL1 S3_0_C15_C1_2
|
|
#define NEOVERSE_V1_ACTLR3_EL1_BIT_47 (ULL(1) << 47)
|
|
|
|
#define NEOVERSE_V1_ACTLR5_EL1 S3_0_C15_C9_0
|
|
#define NEOVERSE_V1_ACTLR5_EL1_BIT_55 (ULL(1) << 55)
|
|
#define NEOVERSE_V1_ACTLR5_EL1_BIT_56 (ULL(1) << 56)
|
|
#define NEOVERSE_V1_ACTLR5_EL1_BIT_61 (ULL(1) << 61)
|
|
|
|
#endif /* NEOVERSE_V1_H */
|