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ac9f4b4da6
The erratum titled “Disabling of data prefetcher with outstanding prefetch TLB miss might cause a deadlock” should not be handled within TF-A. The current workaround attempts to follow option 2 but misapplies it. Specifically, it statically sets PF_MODE to conservative, which is not the recommended approach. According to the erratum documentation, PF_MODE should be configured in conservative mode only when we disable data prefetcher however this is not done in TF-A and thus the workaround is not needed in TF-A. The static setting of PF_MODE in TF-A does not correctly address the erratum and may introduce unnecessary performance degradation on platforms that adopt it without fully understanding its implications. To prevent incorrect or unintended use, the current implementation of this erratum workaround should be removed from TF-A and not adopted by platforms. List of Impacted CPU's with Errata Numbers and reference to SDEN - Cortex-A78 - 2132060 - https://developer.arm.com/documentation/SDEN1401784/latest Cortex-A78C - 2132064 - https://developer.arm.com/documentation/SDEN-2004089/latest Cortex-A710 - 2058056 - https://developer.arm.com/documentation/SDEN-1775101/latest Cortex-X2 - 2058056 - https://developer.arm.com/documentation/SDEN-1775100/latest Cortex-X3 - 2070301 - https://developer.arm.com/documentation/SDEN2055130/latest Neoverse-N2 - 2138953 - https://developer.arm.com/documentation/SDEN-1982442/latest Neoverse-V1 - 2108267 - https://developer.arm.com/documentation/SDEN-1401781/latest Neoverse-V2 - 2331132 - https://developer.arm.com/documentation/SDEN-2332927/latest Change-Id: Icf4048508ae070b2df073cc46c63be058b2779df Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
55 lines
2.1 KiB
C
55 lines
2.1 KiB
C
/*
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* Copyright (c) 2019-2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A78_H
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#define CORTEX_A78_H
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#include <lib/utils_def.h>
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#define CORTEX_A78_MIDR U(0x410FD410)
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/* Cortex-A78 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_A78_BHB_LOOP_COUNT U(32)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)
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#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_A78_ACTLR2_EL1_BIT_0 (ULL(1) << 0)
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#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
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#define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
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#define CORTEX_A78_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
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#define CORTEX_A78_ACTLR3_EL1 S3_0_C15_C1_2
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#define CORTEX_A78_ACTLR5_EL1 S3_0_C15_C9_0
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/*******************************************************************************
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* CPU Activity Monitor Unit register specific definitions.
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******************************************************************************/
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#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4
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#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5
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#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0
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#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1
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#define CORTEX_A78_AMU_GROUP0_MASK U(0xF)
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#define CORTEX_A78_AMU_GROUP1_MASK U(0x7)
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#endif /* CORTEX_A78_H */
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