mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 18:14:24 +00:00
ac9abe7e59
Allow to disable ENABLE_PIE on STM32MP2. BL31 is loaded at the beginning of SYSRAM whatever the options set. Set ENABLE_PIE to 0 by default. This should allow us to reduce BL31 and BL2 size. Change-Id: Ie8c83c9205e81301eb1fdcf24b94216172586630 Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
412 lines
14 KiB
C
412 lines
14 KiB
C
/*
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* Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef STM32MP2_DEF_H
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#define STM32MP2_DEF_H
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#include <common/tbbr/tbbr_img_def.h>
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#ifndef __ASSEMBLER__
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#include <drivers/st/bsec.h>
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#endif
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#include <drivers/st/stm32mp25_rcc.h>
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#ifndef __ASSEMBLER__
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#include <drivers/st/stm32mp2_clk.h>
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#endif
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#include <drivers/st/stm32mp2_pwr.h>
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#include <dt-bindings/clock/stm32mp25-clks.h>
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#include <dt-bindings/clock/stm32mp25-clksrc.h>
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#include <dt-bindings/gpio/stm32-gpio.h>
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#include <dt-bindings/reset/stm32mp25-resets.h>
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#ifndef __ASSEMBLER__
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#include <boot_api.h>
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#include <stm32mp2_private.h>
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#include <stm32mp_common.h>
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#include <stm32mp_dt.h>
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#include <stm32mp_shared_resources.h>
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#endif
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/*******************************************************************************
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* CHIP ID
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******************************************************************************/
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#define STM32MP2_CHIP_ID U(0x505)
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#define STM32MP251A_PART_NB U(0x400B3E6D)
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#define STM32MP251C_PART_NB U(0x000B306D)
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#define STM32MP251D_PART_NB U(0xC00B3E6D)
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#define STM32MP251F_PART_NB U(0x800B306D)
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#define STM32MP253A_PART_NB U(0x400B3E0C)
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#define STM32MP253C_PART_NB U(0x000B300C)
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#define STM32MP253D_PART_NB U(0xC00B3E0C)
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#define STM32MP253F_PART_NB U(0x800B300C)
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#define STM32MP255A_PART_NB U(0x40082E00)
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#define STM32MP255C_PART_NB U(0x00082000)
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#define STM32MP255D_PART_NB U(0xC0082E00)
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#define STM32MP255F_PART_NB U(0x80082000)
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#define STM32MP257A_PART_NB U(0x40002E00)
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#define STM32MP257C_PART_NB U(0x00002000)
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#define STM32MP257D_PART_NB U(0xC0002E00)
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#define STM32MP257F_PART_NB U(0x80002000)
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#define STM32MP2_REV_A U(0x08)
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#define STM32MP2_REV_B U(0x10)
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#define STM32MP2_REV_X U(0x12)
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#define STM32MP2_REV_Y U(0x11)
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#define STM32MP2_REV_Z U(0x09)
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/*******************************************************************************
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* PACKAGE ID
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******************************************************************************/
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#define STM32MP25_PKG_CUSTOM U(0)
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#define STM32MP25_PKG_AL_VFBGA361 U(1)
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#define STM32MP25_PKG_AK_VFBGA424 U(3)
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#define STM32MP25_PKG_AI_TFBGA436 U(5)
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#define STM32MP25_PKG_UNKNOWN U(7)
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/*******************************************************************************
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* STM32MP2 memory map related constants
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******************************************************************************/
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#define STM32MP_SYSRAM_BASE U(0x0E000000)
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#define STM32MP_SYSRAM_SIZE U(0x00040000)
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#define SRAM1_BASE U(0x0E040000)
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#define SRAM1_SIZE_FOR_TFA U(0x00010000)
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#define RETRAM_BASE U(0x0E080000)
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#define RETRAM_SIZE U(0x00020000)
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/* DDR configuration */
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#define STM32MP_DDR_BASE U(0x80000000)
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#define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */
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/* DDR power initializations */
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#ifndef __ASSEMBLER__
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enum ddr_type {
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STM32MP_DDR3,
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STM32MP_DDR4,
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STM32MP_LPDDR4
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};
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#endif
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/* Section used inside TF binaries */
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#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
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/* 512 Bytes reserved for header */
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#define STM32MP_HEADER_SIZE U(0x00000200)
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#define STM32MP_HEADER_BASE (STM32MP_SYSRAM_BASE + \
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STM32MP_PARAM_LOAD_SIZE)
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/* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
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#define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
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#define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \
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STM32MP_PARAM_LOAD_SIZE + \
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STM32MP_HEADER_SIZE)
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#define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \
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(STM32MP_PARAM_LOAD_SIZE + \
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STM32MP_HEADER_SIZE))
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#define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */
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#define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */
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/* Allocate remaining sysram to BL31 Binary only */
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#define STM32MP_BL31_SIZE (STM32MP_SYSRAM_SIZE - \
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STM32MP_BL2_SIZE)
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#define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \
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STM32MP_SYSRAM_SIZE - \
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STM32MP_BL2_SIZE)
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#define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE
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#define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \
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STM32MP_BL2_RO_SIZE)
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#define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \
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STM32MP_SYSRAM_SIZE - \
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STM32MP_BL2_RW_BASE)
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/* BL2 and BL32/sp_min require 4 tables */
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#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
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/*
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* MAX_MMAP_REGIONS is usually:
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* BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup
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*/
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#if defined(IMAGE_BL31)
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#define MAX_MMAP_REGIONS 7
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#else
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#define MAX_MMAP_REGIONS 6
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#endif
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/* DTB initialization value */
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#define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */
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#define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \
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STM32MP_BL2_DTB_SIZE)
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#if defined(IMAGE_BL2)
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#define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE
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#define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE
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#endif
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#if STM32MP_DDR_FIP_IO_STORAGE
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#define STM32MP_DDR_FW_BASE SRAM1_BASE
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#define STM32MP_DDR_FW_DMEM_OFFSET U(0x400)
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#define STM32MP_DDR_FW_IMEM_OFFSET U(0x800)
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#define STM32MP_DDR_FW_MAX_SIZE U(0x8800)
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#endif
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#define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE
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#define STM32MP_FW_CONFIG_BASE STM32MP_SYSRAM_BASE
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#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000))
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#define STM32MP_BL33_MAX_SIZE U(0x400000)
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#define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \
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STM32MP_BL33_MAX_SIZE)
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#define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000)
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#define STM32MP_SOC_FW_CONFIG_MAX_SIZE U(0x10000) /* 64kB for BL31 DT */
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/*******************************************************************************
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* STM32MP2 device/io map related constants (used for MMU)
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******************************************************************************/
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#define STM32MP_DEVICE_BASE U(0x40000000)
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#define STM32MP_DEVICE_SIZE U(0x40000000)
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/*******************************************************************************
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* STM32MP2 RCC
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******************************************************************************/
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#define RCC_BASE U(0x44200000)
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/*******************************************************************************
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* STM32MP2 PWR
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******************************************************************************/
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#define PWR_BASE U(0x44210000)
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/*******************************************************************************
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* STM32MP2 GPIO
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******************************************************************************/
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#define GPIOA_BASE U(0x44240000)
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#define GPIOB_BASE U(0x44250000)
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#define GPIOC_BASE U(0x44260000)
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#define GPIOD_BASE U(0x44270000)
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#define GPIOE_BASE U(0x44280000)
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#define GPIOF_BASE U(0x44290000)
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#define GPIOG_BASE U(0x442A0000)
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#define GPIOH_BASE U(0x442B0000)
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#define GPIOI_BASE U(0x442C0000)
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#define GPIOJ_BASE U(0x442D0000)
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#define GPIOK_BASE U(0x442E0000)
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#define GPIOZ_BASE U(0x46200000)
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#define GPIO_BANK_OFFSET U(0x10000)
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#define STM32MP_GPIOS_PIN_MAX_COUNT 16
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#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
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/*******************************************************************************
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* STM32MP2 UART
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******************************************************************************/
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#define USART1_BASE U(0x40330000)
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#define USART2_BASE U(0x400E0000)
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#define USART3_BASE U(0x400F0000)
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#define UART4_BASE U(0x40100000)
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#define UART5_BASE U(0x40110000)
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#define USART6_BASE U(0x40220000)
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#define UART7_BASE U(0x40370000)
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#define UART8_BASE U(0x40380000)
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#define UART9_BASE U(0x402C0000)
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#define STM32MP_NB_OF_UART U(9)
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/* For UART crash console */
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#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
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/* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */
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#define STM32MP_DEBUG_USART_BASE USART2_BASE
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#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE
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#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR
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#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN
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#define DEBUG_UART_TX_GPIO_PORT 4
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#define DEBUG_UART_TX_GPIO_ALTERNATE 6
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#define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR
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#define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI
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#define DEBUG_UART_TX_EN_REG RCC_USART2CFGR
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#define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN
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#define DEBUG_UART_RST_REG RCC_USART2CFGR
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#define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST
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#define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR
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#define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR
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/*******************************************************************************
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* STM32MP2 SDMMC
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******************************************************************************/
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#define STM32MP_SDMMC1_BASE U(0x48220000)
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#define STM32MP_SDMMC2_BASE U(0x48230000)
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#define STM32MP_SDMMC3_BASE U(0x48240000)
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/*******************************************************************************
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* STM32MP2 BSEC / OTP
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******************************************************************************/
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/*
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* 367 available OTPs, the other are masked
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* - ECIES key: 368 to 375 (only readable by bootrom)
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* - HWKEY: 376 to 383 (never reloadable or readable)
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*/
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#define STM32MP2_OTP_MAX_ID U(0x16F)
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#define STM32MP2_MID_OTP_START U(0x80)
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#define STM32MP2_UPPER_OTP_START U(0x100)
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/* OTP labels */
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#define PART_NUMBER_OTP "part-number-otp"
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#define REVISION_OTP "rev_otp"
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#define PACKAGE_OTP "package-otp"
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#define HCONF1_OTP "otp124"
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#define NAND_OTP "otp16"
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#define NAND2_OTP "otp20"
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#define BOARD_ID_OTP "board-id"
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#define UID_OTP "uid-otp"
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#define LIFECYCLE2_OTP "otp18"
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#define PKH_OTP "otp144"
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#define ENCKEY_OTP "otp260"
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/* OTP mask */
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/* PACKAGE */
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#define PACKAGE_OTP_PKG_MASK GENMASK_32(2, 0)
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#define PACKAGE_OTP_PKG_SHIFT U(0)
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/* IWDG OTP */
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#define HCONF1_OTP_IWDG_HW_POS U(0)
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#define HCONF1_OTP_IWDG_FZ_STOP_POS U(1)
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#define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2)
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/* NAND OTP */
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/* NAND parameter storage flag */
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#define NAND_PARAM_STORED_IN_OTP BIT_32(31)
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/* NAND page size in bytes */
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#define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
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#define NAND_PAGE_SIZE_SHIFT U(29)
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#define NAND_PAGE_SIZE_2K U(0)
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#define NAND_PAGE_SIZE_4K U(1)
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#define NAND_PAGE_SIZE_8K U(2)
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/* NAND block size in pages */
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#define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
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#define NAND_BLOCK_SIZE_SHIFT U(27)
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#define NAND_BLOCK_SIZE_64_PAGES U(0)
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#define NAND_BLOCK_SIZE_128_PAGES U(1)
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#define NAND_BLOCK_SIZE_256_PAGES U(2)
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/* NAND number of block (in unit of 256 blocks) */
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#define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
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#define NAND_BLOCK_NB_SHIFT U(19)
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#define NAND_BLOCK_NB_UNIT U(256)
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/* NAND bus width in bits */
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#define NAND_WIDTH_MASK BIT_32(18)
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#define NAND_WIDTH_SHIFT U(18)
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/* NAND number of ECC bits per 512 bytes */
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#define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
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#define NAND_ECC_BIT_NB_SHIFT U(15)
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#define NAND_ECC_BIT_NB_UNSET U(0)
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#define NAND_ECC_BIT_NB_1_BITS U(1)
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#define NAND_ECC_BIT_NB_4_BITS U(2)
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#define NAND_ECC_BIT_NB_8_BITS U(3)
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#define NAND_ECC_ON_DIE U(4)
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/* NAND number of planes */
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#define NAND_PLANE_BIT_NB_MASK BIT_32(14)
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/* NAND2 OTP */
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#define NAND2_PAGE_SIZE_SHIFT U(16)
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/* NAND2 config distribution */
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#define NAND2_CONFIG_DISTRIB BIT_32(0)
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#define NAND2_PNAND_NAND2_SNAND_NAND1 U(0)
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#define NAND2_PNAND_NAND1_SNAND_NAND2 U(1)
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/* MONOTONIC OTP */
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#define MAX_MONOTONIC_VALUE U(32)
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/* UID OTP */
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#define UID_WORD_NB U(3)
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/* Lifecycle OTP */
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#define SECURE_BOOT_CLOSED_SECURE GENMASK_32(3, 0)
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/*******************************************************************************
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* STM32MP2 TAMP
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******************************************************************************/
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#define PLAT_MAX_TAMP_INT U(5)
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#define PLAT_MAX_TAMP_EXT U(3)
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#define TAMP_BASE U(0x46010000)
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#define TAMP_SMCR (TAMP_BASE + U(0x20))
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#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
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#define TAMP_BKP_REG_CLK CK_BUS_RTC
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#define TAMP_BKP_SEC_NUMBER U(10)
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#define TAMP_COUNTR U(0x40)
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#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
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static inline uintptr_t tamp_bkpr(uint32_t idx)
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{
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return TAMP_BKP_REGISTER_BASE + (idx << 2);
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}
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#endif
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/*******************************************************************************
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* STM32MP2 DDRCTRL
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******************************************************************************/
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#define DDRCTRL_BASE U(0x48040000)
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/*******************************************************************************
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* STM32MP2 DDRDBG
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******************************************************************************/
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#define DDRDBG_BASE U(0x48050000)
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/*******************************************************************************
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* STM32MP2 DDRPHYC
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******************************************************************************/
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#define DDRPHYC_BASE U(0x48C00000)
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/*******************************************************************************
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* Miscellaneous STM32MP1 peripherals base address
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******************************************************************************/
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#define BSEC_BASE U(0x44000000)
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#define DBGMCU_BASE U(0x4A010000)
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#define HASH_BASE U(0x42010000)
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#define RTC_BASE U(0x46000000)
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#define STGEN_BASE U(0x48080000)
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#define SYSCFG_BASE U(0x44230000)
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/*******************************************************************************
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* STM32MP RIF
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******************************************************************************/
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#define RISAB3_BASE U(0x42110000)
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#define RISAB5_BASE U(0x42130000)
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/*******************************************************************************
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* STM32MP CA35SSC
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******************************************************************************/
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#define A35SSC_BASE U(0x48800000)
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/*******************************************************************************
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* REGULATORS
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******************************************************************************/
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/* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
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#define PLAT_NB_RDEVS U(19)
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/* 2 FIXED */
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#define PLAT_NB_FIXED_REGUS U(2)
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/* No GPIO regu */
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#define PLAT_NB_GPIO_REGUS U(0)
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/*******************************************************************************
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* Device Tree defines
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******************************************************************************/
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#define DT_BSEC_COMPAT "st,stm32mp25-bsec"
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#define DT_DDR_COMPAT "st,stm32mp2-ddr"
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#define DT_PWR_COMPAT "st,stm32mp25-pwr"
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#define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc"
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#define DT_SDMMC2_COMPAT "st,stm32mp25-sdmmc2"
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#define DT_UART_COMPAT "st,stm32h7-uart"
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#endif /* STM32MP2_DEF_H */
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